Shanshan Liu

Orcid: 0000-0001-6226-2880

Affiliations:
  • New Mexico State University, Las Cruces, NM, USA


According to our database1, Shanshan Liu authored at least 68 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A High Accuracy and Ultra-Energy-Efficient Zero-Shot-Retraining Seizure Detection Processor.
IEEE J. Solid State Circuits, November, 2024

A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

On the Security of Quotient Filters: Attacks and Potential Countermeasures.
IEEE Trans. Computers, September, 2024

Speed and Conversational Large Language Models: Not All Is About Tokens per Second.
Computer, August, 2024

Adaptive Resolution Inference (ARI): Energy-Efficient Machine Learning for Internet of Things.
IEEE Internet Things J., April, 2024

Joint Learning and Channel Coding for Error-Tolerant IoT Systems Based on Machine Learning.
IEEE Trans. Artif. Intell., January, 2024

On the Privacy of Adaptive Cuckoo Filters: Analysis and Protection.
IEEE Trans. Inf. Forensics Secur., 2024

Concurrent Linguistic Error Detection (CLED) for Large Language Models.
CoRR, 2024

FSNAP: An Ultra-Energy-Efficient Few-Spikes-Neuron Based Reconfigurable SNN Processor Enabling Unified On-Chip Learning and Accuracy-Driven Adaptive Time-Window Tuning.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

14.8 KASP: A 96.8% 10-Keyword Accuracy and 1.68μJ/Classification Keyword Spotting and Speaker Verification Processor Using Adaptive Beamforming and Progressive Wake-Up.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

33.1 A High-Accuracy and Energy-Efficient Zero-Shot-Retraining Seizure-Detection Processor with Hybrid-Feature-Driven Adaptive Processing and Learning-Based Adaptive Channel Selection.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Reducing the Energy Dissipation of Large Language Models (LLMs) with Approximate Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Error-Resilient Data Compression With Tunstall Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

Attacking the Privacy of Approximate Membership Check Filters by Positive Concentration.
IEEE Trans. Computers, May, 2023

Tolerance of Siamese Networks (SNs) to Memory Errors: Analysis and Design.
IEEE Trans. Computers, April, 2023

Delta Sigma Modulator-Based Dividers for Accurate and Low Latency Stochastic Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips.
IEEE Trans. Sustain. Comput., 2023

A Technique for Approximate Communication in Network-on-Chips for Image Classification.
IEEE Trans. Emerg. Top. Comput., 2023

On the Privacy of Counting Bloom Filters.
IEEE Trans. Dependable Secur. Comput., 2023

On the Privacy of Counting Bloom Filters Under a Black-Box Attacker.
IEEE Trans. Dependable Secur. Comput., 2023

Concurrent Classifier Error Detection (CCED) in Large Scale Machine Learning Systems.
CoRR, 2023

Feature-Embedding Triplet Networks with a Separately Constrained Loss Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Integrating Delta Modulation and Stochastic Computing for Real-time Machine Learning based Heartbeats Monitoring in Wearable Systems.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Attacking Adaptive Cuckoo Filters: Too Much Adaptation Can Kill You.
IEEE Trans. Netw. Serv. Manag., December, 2022

Computing the Similarity Estimate Using Approximate Memory.
IEEE Trans. Emerg. Top. Comput., 2022

Guest Editorial: Special Section on "To be Safe and Dependable in the Era of Artificial Intelligence: Emerging Techniques for Trusted and Reliable Machine Learning".
IEEE Trans. Emerg. Top. Comput., 2022

On the Security of the K Minimum Values (KMV) Sketch.
IEEE Trans. Dependable Secur. Comput., 2022

Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog.
IEEE Trans. Dependable Secur. Comput., 2022

A Delta Sigma Modulator-Based Stochastic Divider.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Selective Neuron Re-Computation (SNRC) for Error-Tolerant Neural Networks.
IEEE Trans. Computers, 2022

Approximate Network-on-Chips with Application to Image Classification.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2022

Tampering Attack Detection in Analog to Feature Converter for Wearable Biosensor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP).
IEEE Trans. Emerg. Top. Comput., 2021

Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2021

Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design.
IEEE Trans. Emerg. Top. Comput., 2021

Reduced Precision Redundancy for Reliable Processing of Data.
IEEE Trans. Emerg. Top. Comput., 2021

Stochastic Dividers for Low Latency Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets.
IEEE Trans. Aerosp. Electron. Syst., 2021

Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).
Integr., 2021

Less-is-Better Protection (LBP) for memory errors in <i>k</i>NNs classifiers.
Future Gener. Comput. Syst., 2021

Analyzing and Assessing Pollution Attacks on Bloom Filters: Some Filters are More Vulnerable than Others.
Proceedings of the 17th International Conference on Network and Service Management, 2021

2020
Error-Tolerant Computation for Voting Classifiers With Multiple Classes.
IEEE Trans. Veh. Technol., 2020

Codes for Limited Magnitude Error Correction in Multilevel Cell Memories.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Result-Based Re-computation for Error-Tolerant Classification by a Support Vector Machine.
IEEE Trans. Artif. Intell., 2020

Scheme for periodical concurrent fault detection in parallel CRC circuits.
IET Comput. Digit. Tech., 2020

Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes.
IEEE Trans. Computers, 2019

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.
Microelectron. Reliab., 2018

2017
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes.
IEEE Trans. Reliab., 2017

Single Event Transient Tolerant Bloom Filter Implementations.
IEEE Trans. Computers, 2017

A method to recover critical bits under a double error in SEC-DED protected memories.
Microelectron. Reliab., 2017

Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).
Microelectron. Reliab., 2017

Low redundancy matrix-based codes for adjacent error correction with parity sharing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Extend orthogonal Latin square codes for 32-bit data protection in memory applications.
Microelectron. Reliab., 2016

2015
Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.
IEEE Trans. Reliab., 2015

Novel technique for P-hit single-event transient mitigation using enhance dummy transistor.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Fault Secure Encoder and Decoder Designs for Matrix Codes.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2011
Mitigation of permanent faults in adaptive equalizers.
Microelectron. Reliab., 2011


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