Shanlin Xiao
Orcid: 0000-0002-1250-8704
According to our database1,
Shanlin Xiao
authored at least 35 papers
between 2016 and 2025.
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Collaborative distances:
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Bibliography
2025
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
2024
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint.
IEEE Trans. Very Large Scale Integr. Syst., October, 2024
SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule.
IEEE Trans. Biomed. Circuits Syst., October, 2024
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024
Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer.
Proceedings of the IEEE International Conference on Acoustics, 2024
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks.
CoRR, 2023
Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Microelectron. J., 2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing.
J. Electronic Imaging, 2021
High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning.
Neurocomputing, 2021
Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks.
IEICE Electron. Express, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
2020
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Biomed. Circuits Syst., 2020
BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network.
CoRR, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Proceedings of the 25th International Conference on Pattern Recognition, 2020
2018
A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2018
2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016