Shan-Chih Tsou

According to our database, Shan-Chih Tsou authored at least 5 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 339-nW 32.768-kHz DFLL-Based Reference Clock Generator with an Embedded Temperature Sensor.

Shuan Yang, Tai-Hong Chen, Yu-Chi Wang, Chia-Hsi Fang, Chun-Yu Lin, Shan-Chih Tsou, Shon-Hang Wen, Kuan-Dar Chen, Tsung-Hsien Lin

Proceedings of the 21st International SoC Design Conference, 2024

2023

A 6nW 30.8kHz Relaxation Oscillator with Sampling Bias-Free RC Circuit and Dynamic Power Scaling in a 12nm FinFET.

Fan-Wei Liao, Shan-Chih Tsou, Chien-Sheng Chao

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2019

A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET.

Ying-Zu Lin, Chin-Yu Lin, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016

A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS.

Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2006

A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay.

Shan-Chih Tsou, Chin-Fu Li, Po-Chiun Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2006