Shakti Kapoor

According to our database1, Shakti Kapoor authored at least 9 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2021
A matrix math facility for Power ISA(TM) processors.
CoRR, 2021

2015
Debugging post-silicon fails in the IBM POWER8 bring-up lab.
IBM J. Res. Dev., 2015

2014
Post-Silicon Validation of the IBM POWER8 Processor.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2010
Bridging pre-silicon verification and post-silicon validation.
Proceedings of the 47th Design Automation Conference, 2010

2007
Feasibility study of MPI implementation on the heterogeneous multi-core cell BE<sup>TM</sup> architecture.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

A Synchronous Mode MPI Implementation on the Cell BE<sup>TM</sup> Architecture.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

A Buffered-Mode MPI Implementation for the Cell BE<sup>TM</sup> Processor.
Proceedings of the Computational Science, 2007

Challenges in post-silicon verification of IBM's Cell/B.E. and other game processors.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Optimization of Collective Communication in Intra-cell MPI.
Proceedings of the High Performance Computing, 2007


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