Shaker Sarwary

According to our database1, Shaker Sarwary authored at least 4 papers between 1996 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2016
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Conclusively verifying clock-domain crossings in very large hardware designs.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

1996



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