Shahzad Ahmad Butt

Orcid: 0000-0002-9747-221X

According to our database1, Shahzad Ahmad Butt authored at least 9 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2018
Design and hardware implementation of the code and carrier tracking block for an inter-operable GNSS receiver.
Proceedings of the 2018 Annual IEEE International Systems Conference, 2018

2016
Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis.
ACM Trans. Embed. Comput. Syst., 2016

2015
Model-based High Level Synthesis and Design Space Exploration.
PhD thesis, 2015

2014
Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework.
J. Electronic Imaging, 2014

2013
Design of a pseudo-log image transform IP in an HLS-based memory management framework.
Proceedings of the Real-Time Image and Video Processing 2013, 2013

Design space exploration and synthesis for digital signal processing algorithms from Simulink models.
Proceedings of the 8th International Design and Test Symposium, 2013

2012
Designing parameterized signal processing ips for high level synthesis in a model based design environment.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Model-based rapid prototyping of multirate digital signal processing algorithms.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011


  Loading...