Shahrzad Naraghi

According to our database, Shahrzad Naraghi authored at least 6 papers between 2009 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2015

Session 2 - Low power analog.

Shahrzad Naraghi, Alessandro Piovaccari

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2012

A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter.

Praveen K. Yenduri, Aaron Z. Rocca, Aswin S. Rao, Shahrzad Naraghi, Michael P. Flynn, Anna C. Gilbert

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

2011

Rand PPM: A lowpower compressive sampling analog to digital converter.

Praveen K. Yenduri, Anna C. Gilbert, Michael P. Flynn, Shahrzad Naraghi

Proceedings of the IEEE International Conference on Acoustics, 2011

2010

A 9-bit, 14 μW and 0.06 mm ² Pulse Position Modulation ADC in 90 nm Digital CMOS.

Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn

IEEE J. Solid State Circuits, 2010

2009

A 9b 14µW 0.06mm² PPM ADC in 90nm digital CMOS.

Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn

Proceedings of the IEEE International Solid-State Circuits Conference, 2009