Shahrzad Mirkhani
According to our database1,
Shahrzad Mirkhani
authored at least 19 papers
between 2001 and 2019.
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Bibliography
2019
Proceedings of the 10th International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2019
2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
EAGLE: A regression model for fault coverage estimation using a simulation based metric.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the 2012 IEEE International Test Conference, 2012
2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.
Proceedings of the Forum on specification and Design Languages, 2007
2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electron. Test., 2004
2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001