Shahin Golshan
According to our database1,
Shahin Golshan
authored at least 10 papers
between 2007 and 2012.
Collaborative distances:
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Bibliography
2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
On leakage power optimization in clock tree networks for ASICs and general-purpose processors.
Sustain. Comput. Informatics Syst., 2011
Process variation aware system-level load assignment for total energy minimization using stochastic ordering.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
2009
Proceedings of the Design, Automation and Test in Europe, 2009
2007
Proceedings of the 44th Design Automation Conference, 2007