Shahar Kvatinsky

Orcid: 0000-0001-7277-7271

According to our database1, Shahar Kvatinsky authored at least 109 papers between 2011 and 2024.

Collaborative distances:

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Bibliography

2024
TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism Memristors.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics.
IEEE Trans. Emerg. Top. Comput., 2024

Roadmap to Neuromorphic Computing with Emerging Technologies.
CoRR, 2024

Transimpedance Amplifier with Automatic Gain Control Based on Memristors for Optical Signal Acquisition.
CoRR, 2024

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023

AritPIM: High-Throughput In-Memory Arithmetic.
IEEE Trans. Emerg. Top. Comput., 2023

TDPP: Two-Dimensional Permutation-Based Protection of Memristive Deep Neural Networks.
CoRR, 2023

CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design.
CoRR, 2023

ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration.
CoRR, 2023

FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication.
CoRR, 2023

Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

On Consistency for Bulk-Bitwise Processing-in-Memory.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
Superconductive Logic Using 2ϕ - Josephson Junctions With Half Flux Quantum Pulses.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

MultPIM: Fast Stateful Multiplication for Processing-in-Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems.
ACM J. Emerg. Technol. Comput. Syst., 2022

Stateful Logic using Phase Change Memory.
CoRR, 2022

Review of security techniques for memristor computing systems.
CoRR, 2022

Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM.
CoRR, 2022

PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory.
CoRR, 2022

Making Real Memristive Processing-in-Memory Faster and Reliable.
CoRR, 2022

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics.
CoRR, 2022

Memristive deep belief neural network by silicon synapses.
CoRR, 2022

Physical based compact model of Y-Flash memristor for neuromorphic computation.
CoRR, 2022

Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices.
Adv. Intell. Syst., 2022

HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Enhancing Security of Memristor Computing System Through Secure Weight Mapping.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Undergraduate Students' Attitudes Toward an Engineering Course that Integrates Several Levels of Abstraction.
Proceedings of the Learning in the Age of Digital and Green Transition, 2022

2021
Radiofrequency Switches Based on Emerging Resistive Memory Technologies - A Survey.
Proc. IEEE, 2021

Improving Efficiency and Lifetime of Logic-in-Memory by Combining IMPLY and MAGIC Families.
J. Syst. Archit., 2021

multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures.
ACM J. Emerg. Technol. Comput. Syst., 2021

(V)TEAM for SPICE Simulation of Memristive Devices With Improved Numerical Performance.
IEEE Access, 2021

Making Memristive Processing-in-Memory Reliable.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

FiltPIM: In-Memory Filter for DNA Sequencing.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Cytomorphic Electronics With Memristors for Modeling Fundamental Genetic Circuits.
IEEE Trans. Biomed. Circuits Syst., 2020

X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.
Proceedings of the VLSI-SoC: Design Trends, 2020

abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

A Pipelined Memristive Neural Network Analog-to-Digital Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters.
Proceedings of the European Conference on Circuit Theory and Design, 2020

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic.
Microelectron. J., 2019

Adaptive programming in multi-level cell ReRAM.
Microelectron. J., 2019

CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM.
IEEE Micro, 2019

MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks.
CoRR, 2019

The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm.
CoRR, 2019

Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Real Processing-In-Memory with Memristive Memory Processing Unit.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019

A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Performing Memristor-Aided Logic (MAGIC) using STT-MRAM.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Logarithmic Neural Network Data Converters using Memristors for Biomedical Applications.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU).
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

A Taxonomy and Evaluation Framework for Memristive Logic.
Proceedings of the Handbook of Memristor Networks., 2019

2018
Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture.
IEEE Trans. Emerg. Top. Comput. Intell., 2018

TIME - Tunable Inductors Using MEmristors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

IMAGING: In-Memory AlGorithms for Image processiNG.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing.
IEEE Micro, 2018

Analysis of the row grounding technique in a memristor-based crossbar array.
Int. J. Circuit Theory Appl., 2018

DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Real-Time Trainable Data Converters for General Purpose Applications.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Practical challenges in delivering the promises of real processing-in-memory machines.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era.
IEEE Des. Test, 2017

Memristive logic: A framework for evaluation and comparison.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

An RF memristor model and memristive single-pole double-throw switches.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Rate-compatible and high-throughput architecture designs for encoding LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Towards a memristive hardware secure hash function (MemHash).
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Memristor for computing: Myth or reality?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Modeling biochemical reactions and gene networks with memristors.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Information-Theoretic Sneak-Path Mitigation in Memristor Crossbar Arrays.
IEEE Trans. Inf. Theory, 2016

Resistive GP-SIMD Processing-In-Memory.
ACM Trans. Archit. Code Optim., 2016

A Systematic Approach to Blocking Convolutional Neural Networks.
CoRR, 2016

Logic with Unipolar Memristors - Circuits and Design Methodology.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Logic design with unipolar memristors.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Memory Processing Unit for in-memory processing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Evaluating programmable architectures for imaging and vision applications.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Improving energy efficiency of DRAM by exploiting half page row access.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Write sneak-path constraints avoiding disturbs in memristor crossbar arrays.
Proceedings of the IEEE International Symposium on Information Theory, 2016

A fully analog memristor-based neural network with online gradient training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Multistate Register Based on Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training.
IEEE Trans. Neural Networks Learn. Syst., 2015

VTEAM: A General Model for Voltage-Controlled Memristors.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Resistive Associative Processor.
IEEE Comput. Archit. Lett., 2015

2014
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies.
IEEE Trans. Very Large Scale Integr. Syst., 2014

MAGIC - Memristor-Aided Logic.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Logic operations in memory using a memristive Akers array.
Microelectron. J., 2014

Memristor-Based Multithreading.
IEEE Comput. Archit. Lett., 2014

2013
TEAM: ThrEshold Adaptive Memristor Model.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Sneak-path constraints in memristor crossbar arrays.
Proceedings of the 2013 IEEE International Symposium on Information Theory, 2013

2011
Memristor-based IMPLY logic design procedure.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011


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