Shaahin Hessabi
Orcid: 0000-0003-3193-2567
According to our database1,
Shaahin Hessabi
authored at least 98 papers
between 1995 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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Bibliography
2025
Poster: Unified Fog Node Utilization for Multiple Content Providers through Cluster-Based Cooperative Caching.
Proceedings of the 25th IEEE International Symposium on a World of Wireless, 2025
2024
ACM Trans. Archit. Code Optim., September, 2024
IEEE Trans. Mob. Comput., July, 2024
Cluster-based cooperative fog caching for scalable coded videos of multiple content providers.
Internet Things, 2024
2023
Digit., 2023
Proceedings of the 24st Asia-Pacific Network Operations and Management Symposium, 2023
2022
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
Tolerating Permanent Faults With Low-Energy Overhead in Multicore Mixed-Criticality Systems.
IEEE Trans. Emerg. Top. Comput., 2022
HFOS<sub>L</sub>: hyper scale fast optical switch-based data center network with L-level sub-network.
Telecommun. Syst., 2022
A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues.
IEEE Access, 2022
2021
Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators.
IEEE Trans. Emerg. Top. Comput., 2021
REALISM: Reliability-aware energy management in multi-level mixed-criticality systems with service level degradation.
J. Syst. Archit., 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Comput. Electr. Eng., 2020
Aging-Aware Context Switching in Multicore Processors Based on Workload Classification.
IEEE Comput. Archit. Lett., 2020
2019
On the Scheduling of Energy-Aware Fault-Tolerant Mixed-Criticality Multicore Systems with Service Guarantee Exploration.
IEEE Trans. Parallel Distributed Syst., 2019
ACM Trans. Archit. Code Optim., 2019
Nano Commun. Networks, 2019
CoRR, 2019
2018
DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture.
IEEE Trans. Computers, 2018
Microprocess. Microsystems, 2018
SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2017
J. Parallel Distributed Comput., 2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
2016
A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard.
J. Circuits Syst. Comput., 2016
Comput. Electr. Eng., 2016
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design.
IET Comput. Digit. Tech., 2015
Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality.
IET Comput. Digit. Tech., 2015
Comput. Electr. Eng., 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
IEEE Trans. Computers, 2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
2013
Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip.
Int. J. Adapt. Resilient Auton. Syst., 2013
IET Comput. Digit. Tech., 2013
2012
Microprocess. Microsystems, 2012
J. Parallel Distributed Comput., 2012
IET Comput. Digit. Tech., 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses.
Microprocess. Microsystems, 2011
Hierarchical opto-electrical on-chip network for future multiprocessor architectures.
J. Syst. Archit., 2011
Proceedings of the NOCS 2011, 2011
Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC.
Proceedings of the 25th IEEE International Conference on Advanced Information Networking and Applications Workshops, 2011
2010
Proceedings of the 18th Euromicro Conference on Parallel, 2010
Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model.
Microprocess. Microsystems, 2008
J. Circuits Syst. Comput., 2008
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the Euro-Par 2008, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus.
Proceedings of the Advances in Computer Science and Engineering, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008
2007
Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems.
J. Comput. Syst. Sci., 2007
Int. J. Web Grid Serv., 2007
Comput. Electr. Eng., 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Proceedings of the Sixth IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2006), 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
2005
An Accurate Fir Approximation of Ideal Fractional Delay Filter with Complex Coefficients in Hilbert Space.
J. Circuits Syst. Comput., 2005
Design of Variable Fractional Delay Fir Filters with Csd Coefficients Using Genetic Algorithm.
J. Circuits Syst. Comput., 2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems.
Proceedings of the Dependable Computing, Second Latin-American Symposium, 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs.
J. Univers. Comput. Sci., 2004
Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models.
Proceedings of the 2004 Design, 2004
A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the Forum on specification and Design Languages, 2003
1995
Differential BiCMOS logic circuits: fault characterization and design-for-testability.
IEEE Trans. Very Large Scale Integr. Syst., 1995