Seyyed Hossein Seyyedaghaei Rezaei

Orcid: 0000-0002-6310-8954

According to our database1, Seyyed Hossein Seyyedaghaei Rezaei authored at least 7 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Smart Memory: Deep Learning Acceleration in 3D-Stacked Memories.
IEEE Comput. Archit. Lett., 2024

2023
NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
Chapter Seven - Power-efficient network-on-chip design by partial topology reconfiguration.
Adv. Comput., 2022

2020
NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories.
IEEE Comput. Archit. Lett., 2020

2016
Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip.
IEEE Comput. Archit. Lett., 2016

A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Fault-tolerant 3-D network-on-chip design using dynamic link sharing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016


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