Seyyed Hossein Seyyedaghaei Rezaei

According to our database, Seyyed Hossein Seyyedaghaei Rezaei authored at least 7 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Smart Memory: Deep Learning Acceleration in 3D-Stacked Memories.

Seyyed Hossein Seyyedaghaei Rezaei, Parham Zilouchian Moghaddam, Mehdi Modarressi

IEEE Comput. Archit. Lett., 2024

2023

NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures.

Ali Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Masoud Daneshtalab

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022

Chapter Seven - Power-efficient network-on-chip design by partial topology reconfiguration.

Mehdi Modarressi, Seyyed Hossein Seyyedaghaei Rezaei

Adv. Comput., 2022

2020

NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories.

Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Rachata Ausavarungnirun, Mohammad Sadrosadati, Onur Mutlu, Masoud Daneshtalab

IEEE Comput. Archit. Lett., 2020

2016

Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip.

Seyyed Hossein Seyyedaghaei Rezaei, Abbas Mazloumi, Mehdi Modarressi, Pejman Lotfi-Kamran

IEEE Comput. Archit. Lett., 2016

A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing.

Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Masoud Daneshtalab, Shervin Roshanisefat

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Fault-tolerant 3-D network-on-chip design using dynamic link sharing.

Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Reza Yazdani Aminabadi, Masoud Daneshtalab

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016