Seyedhamidreza Motaman

Orcid: 0000-0003-4475-996X

According to our database1, Seyedhamidreza Motaman authored at least 15 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays.
CoRR, 2023

2022
Addressing Resiliency of In-Memory Floating Point Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2022

2019
Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM.
IEEE Trans. Emerg. Top. Comput., 2019

A Perspective on Test Methodologies for Supervised Machine Learning Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

2018
VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.
ACM J. Emerg. Technol. Comput. Syst., 2018

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Novel application of spintronics in computing, sensing, storage and cybersecurity.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2016
Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Overview of Circuits, Systems, and Applications of Spintronics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2015
A novel slope detection technique for robust STTRAM sensing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Impact of process-variations in STTRAM and adaptive boosting for robustness.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Synergistic circuit and system design for energy-efficient and robust domain wall caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014


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