Seyedhamidreza Motaman
Orcid: 0000-0003-4475-996X
According to our database1,
Seyedhamidreza Motaman
authored at least 15 papers
between 2014 and 2023.
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Bibliography
2023
A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays.
CoRR, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
2019
IEEE Trans. Emerg. Top. Comput., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.
ACM J. Emerg. Technol. Comput. Syst., 2018
Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2016
Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Synergistic circuit and system design for energy-efficient and robust domain wall caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014