Seyedeh Fatemeh Ghamkhari

Orcid: 0000-0002-9925-1058

According to our database1, Seyedeh Fatemeh Ghamkhari authored at least 5 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Bibliography

2022
AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A power-performance partitioning approach for low-power DA-based FIR filter design with emphasis on datapath and controller.
Int. J. Circuit Theory Appl., 2022

2021
A New Low Power Schema for Stream Processors Front-End with Power-Aware DA-Based FIR Filters by Investigation of Image Transitions Sparsity.
Circuits Syst. Signal Process., 2021

2020
Design and Implementation of Reconfigurable Integrated FPGA-based PSK Demodulator.
Proceedings of the 10th International Symposium on Telecommunications, 2020

2014
A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation.
Circuits Syst. Signal Process., 2014


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