Seyed-Sajad Ahmadpour
Orcid: 0000-0003-2462-8030
According to our database1,
Seyed-Sajad Ahmadpour
authored at least 21 papers
between 2018 and 2025.
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Collaborative distances:
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Online presence:
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Bibliography
2025
Secure Quantum-based Adder Design for Protecting Machine Learning Systems Against Side-Channel Attacks.
Appl. Soft Comput., 2025
2024
J. Supercomput., January, 2024
Design and implementation of a nano-scale high-speed multiplier for signal processing applications.
Nano Commun. Networks, 2024
A new energy-efficient design for quantum-based multiplier for nano-scale devices in internet of things.
Comput. Electr. Eng., 2024
2023
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm.
IEEE Des. Test, October, 2023
An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots.
Comput. Electr. Eng., September, 2023
An Efficient Design of Multiplier for Using in Nano-Scale IoT Systems Using Atomic Silicon.
IEEE Internet Things J., August, 2023
A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation.
Nano Commun. Networks, June, 2023
J. Supercomput., March, 2023
Nano-design of ultra-efficient reversible block based on quantum-dot cellular automata.
Frontiers Inf. Technol. Electron. Eng., March, 2023
2022
An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform.
Nano Commun. Networks, December, 2022
Efficient designs of quantum-dot cellular automata multiplexer and RAM with physical proof along with power analysis.
J. Supercomput., 2022
2021
Circuits Syst. Signal Process., 2021
Comput. Electr. Eng., 2021
2020
The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate.
J. Supercomput., 2020
A novel ultra-dense and low-power structure for fault-tolerant three-input majority gate in QCA technology.
Concurr. Comput. Pract. Exp., 2020
An efficient fault-tolerant arithmetic logic unit using a novel fault-tolerant 5-input majority gate in quantum-dot cellular automata.
Comput. Electr. Eng., 2020
2019
Correction to: A novel fault-tolerant multiplexer in quantum-dot cellular automata technology.
J. Supercomput., 2019
Nano Commun. Networks, 2019
Int. J. Circuit Theory Appl., 2019
2018
J. Supercomput., 2018