Seyed Mojtaba Atarodi

Orcid: 0000-0002-8090-109X

According to our database1, Seyed Mojtaba Atarodi authored at least 58 papers between 1999 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Design & Implementation of High Dynamic Range Current Measurement System for IoT Applications.
IEEE Trans. Instrum. Meas., 2022

2021
A Tree-Structured LoRa Network for Energy Efficiency.
IEEE Internet Things J., 2021

2020
An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping.
IEEE Trans. Circuits Syst., 2020

A Low-Power Clock Generator with a Wide Frequency Tuning Range and Low Temperature Variation: Analysis and Design.
J. Circuits Syst. Comput., 2020

2018
A common gate LNA with negative resistance for noise reduction.
Microelectron. J., 2018

2015
Analysis of imperfections in N-phase high-Q band-pass filters.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
An N-Path Enhanced-Q Tunable Filter With Reduced Harmonic Fold Back Effects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - µm CMOS technology.
Int. J. Circuit Theory Appl., 2012

Noise Canceling Balun-LNA with Enhanced IIP2 and IIP3 for Digital TV Applications.
IEICE Trans. Electron., 2012

2011
A sub 1 V high PSRR CMOS bandgap voltage reference.
Microelectron. J., 2011

A 6-bit active digital phase shifter.
IEICE Electron. Express, 2011

Low phase noise on-chip oscillator for implantable biomedical applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Behavioral modeling of clock feed-through and channel charge injection non-ideal effects in SIMULINK for switched-capacitor integrator.
Simul. Model. Pract. Theory, 2010

2009
Second and third-order distortion suppression technique for noise canceling CMOS LNAs.
IEICE Electron. Express, 2009

A noise shaped flash time to digital converter for all digital frequency synthesizers.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance.
IET Circuits Devices Syst., 2008

New low voltage, high PSRR, CMOS bandgap voltage reference.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Cellular design for a dense RFID reader environment.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Power Optimized Base-Band Circuitry for the Low-IF Receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-Power CMOS Low-IF Receiver Front-End for 2450-MHz Band IEEE 802.15.4 ZigBee Standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-µm CMOS Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-Area, 0.18µm CMOS, 10Gb/s Optical Receiver Analog Front End.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 1/4 rate linear phase detector for PLL-based CDR circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A technique to suppress tail current flicker noise in CMOS LC VCOs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A compact low power mixed-signal equalizer for gigabit Ethernet applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A low-power, multichannel gated oscillator-based CDR for short-haul applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.
Proceedings of the 2005 Design, 2005

A fractional delay-locked loop for on chip clock generation applications.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A fast converging algorithm for network echo cancellation.
IEEE Signal Process. Lett., 2004

A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A duty cycle control circuit for high speed applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Design and optimization of a high PSRR CMOS bandgap voltage reference.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A new full CMOS 2.5 V two-stage line driver with variable gain for ADSL applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A new low voltage precision CMOS current reference with no external components.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Structured design of an integrated subscriber line interface system and circuit.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A compact biquadratic g<sub>m</sub>-C filter structure for low-voltage and high frequency applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A new low-power sigma-delta modulator with the reduced number of op-amps for speech band applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An ultra low-voltage Gm-C filter for video applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1-volt, high PSRR, CMOS bandgap voltage reference.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1.8-v high-speed 13-bit pipelined analog to digital converter for digital IF applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A compact, low power, fully integrated clock frequency doubler.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A 1.5-V 14-bit CMOS DAC with a new self-calibration technique for wireless communication systems.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A novel, low voltage, precision CMOS current reference with no external components.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
A low-power subscriber line interface circuit in a high-voltage CMOS technology.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A high dynamic range CMOS variable gain filter for ADSL.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Composite PNLMS & NLMS adaptation: a new method for network echo cancellation.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002

2000
A 1.5-V supply, video range frequency, Gm-C filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A high dynamic-range, self-tuned Gm-C filter for video-range applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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