Seungwhun Paik
According to our database1,
Seungwhun Paik
authored at least 22 papers
between 2008 and 2016.
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Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2016
Integr., 2016
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks.
J. Circuits Syst. Comput., 2011
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Wakeup synthesis and its buffered tree construction for power gating circuit designs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.
Proceedings of the 45th Design Automation Conference, 2008
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008