Seungkyu Choi
Orcid: 0000-0002-3125-9707
According to our database1,
Seungkyu Choi
authored at least 19 papers
between 2011 and 2024.
Collaborative distances:
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Bibliography
2024
ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
SONA: An Accelerator for Transform-Domain Neural Networks with Sparse-Orthogonal Weights.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023
2022
Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks.
IEEE Trans. Computers, 2022
A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type.
IEEE Trans. Computers, 2022
Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNN.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2020
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices.
IEEE J. Solid State Circuits, 2020
A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2014
Wirel. Pers. Commun., 2014
2011
IEICE Trans. Commun., 2011