Seungha Roh

Orcid: 0000-0002-5429-4812

According to our database¹, Seungha Roh authored at least 9 papers between 2021 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2024

A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

2023

A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

An 80-Gb/s PAM-4 Simultaneous Bidirectional Transceiver With Hybrid Adaptation Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS.

[BibT_eX]

[DOI]

Seungha Roh

Moon-Chul Choi

Deog-Kyoon Jeong

Proceedings of the 18th International SoC Design Conference, 2021

A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Seungha Roh

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