Seung-Wook Kwack
According to our database1,
Seung-Wook Kwack
authored at least 6 papers
between 2006 and 2014.
Collaborative distances:
Collaborative distances:
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Bibliography
2014
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2009
A high speed graphics DRAM with low power and low noise data bus inversion in 54nm CMOS.
IEICE Electron. Express, 2009
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2006
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006