Seung-Hyuk Kang

Orcid: 0000-0003-4270-9918

Affiliations:

Qualcomm, San Diego, CA, USA

According to our database¹, Seung-Hyuk Kang authored at least 40 papers between 2009 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2021

Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

STT-MRAM Sensing: A Review.

[BibT_eX]

[DOI]

Taehui Na

Seung-Hyuk Kang

Seong-Ook Jung

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019

Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

2016

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Equalization scheme analysis for high-density spin transfer torque random access memory.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Area-optimal sensing circuit designs in deep submicrometer STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Architecture design with STT-RAM: Opportunities and challenges.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Reference-circuit analysis for high-bandwidth spin transfer torque random access memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Split-Path Sensing Circuit for Spin Torque Transfer MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

An MTJ-based non-volatile flip-flop for high-performance SoC.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2014

Unified embedded non-volatile memory for emerging mobile markets.

[BibT_eX]

[DOI]

Kangho Lee

Jimmy J. Kan

Seung-Hyuk Kang

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

High-performance low-power magnetic tunnel junction based non-volatile flip-flop.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A comparative study of STT-MTJ based non-volatile flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM).

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Probabilistically Programmed STT-MRAM.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

2011

Sensing margin trend with technology scaling in MRAM.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2011

MTJ based non-volatile flip-flop in deep submicron technology.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2010

2009

Pathfinding for 22nm CMOS designs using Predictive Technology Models.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Seung-Hyuk Kang

Timeline

Legend:

Links

Online presence:

On csauthors.net:

Bibliography

Loading...