Seung Eun Lee

Orcid: 0000-0003-3817-4383

According to our database1, Seung Eun Lee authored at least 78 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

On-Device Eye Tracking System with Dual Lightweight AI Processor.
Proceedings of the 21st International SoC Design Conference, 2024

Accelerating Embedded WebAssembly Based on FPGA.
Proceedings of the 21st International SoC Design Conference, 2024

Point Cloud Clustering System with DBSCAN Algorithm for Low-Resolution LiDAR.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023
The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension.
IEEE Access, 2023

Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture.
Proceedings of the 20th International SoC Design Conference, 2023

The Design of Embedded Fuzzy Logic Controller for Autonomous Mobile Robots.
Proceedings of the 20th International SoC Design Conference, 2023

RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Embedded Monitoring System for Preventing Lonely Death Based on Edge AI.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023

A Real-Time Reconfigurable AI Processor Based on FPGA.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023

AI Processor based Data Correction for Enhancing Accuracy of Ultrasonic Sensor.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Evaluation of Posit Arithmetic on Machine Learning based on Approximate Exponential Functions.
Proceedings of the 19th International SoC Design Conference, 2022

Reconfigurable Stochastic Computing Architecture for Computationally Intensive Applications.
Proceedings of the 19th International SoC Design Conference, 2022

Robot-on-Chip: Computing on a Single Chip for an Autonomous Robot.
Proceedings of the IEEE International Conference on Consumer Electronics, 2022

A Local Interconnect Network Controller for Resource-Constrained Automotive Devices.
Proceedings of the IEEE International Conference on Consumer Electronics, 2022

An Architecture for Resilient Federated Learning through Parallel Recognition.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
Crime Prevention System: Crashing Window Sound Detection Using AI Processor.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

Vision-based Parking Occupation Detecting with Embedded AI Processor.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

2020
Design of Low-Power SoC for Wearable Healthcare Device.
J. Circuits Syst. Comput., 2020

Energy Efficient and Low-Cost Server Architecture for Hadoop Storage Appliance.
KSII Trans. Internet Inf. Syst., 2020

DozyBand: Bandwidth Adaptation With Lightweight Signaling for Energy Efficient Wireless Communications in IEEE 802.11ac WLANs.
IEEE Commun. Lett., 2020

Design of 32-bit Processor for Embedded Systems.
Proceedings of the International SoC Design Conference, 2020

Stochastic Computing based AI System for Mobile Devices.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

2019
Flexible Embedded AI System with High-speed Neuromorphic Controller.
Proceedings of the 2019 International SoC Design Conference, 2019

Remote In-System Reconfiguration for Automotive Device.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

An FPGA-based Electronic Control Unit for Automotive Systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2D Line Draw Hardware Accelerator for Tiny Embedded Processor in Consumer Electronics.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2017
Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression.
IEICE Electron. Express, 2017

Design of CAN - CAN FD bridge for in-vehicle network.
Proceedings of the International SoC Design Conference, 2017

Real-time PPG monitoring system for mobile healthcare devices.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2017

In-vehicle CAN FD Network for smart wearable devices.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017

2016
A Hardware Scheduler for Multicore Block Cipher Processor.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

CAN FD controller for in-vehicle system.
Proceedings of the International SoC Design Conference, 2016

Design of an area-efficient hardware filter for embedded system.
Proceedings of the International SoC Design Conference, 2016

Live demonstration: CAN FD controller for in-vehicle network.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Live demonstration: An FPGA based hardware compression accelerator for Hadoop system.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Live demonstration: AHB based digital filter for low power mobile healthcare system.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Secure communication system for wearable devices wireless intra body communication.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

2014
Compression Accelerator for Hadoop Appliance.
Proceedings of the Internet of Vehicles - Technologies and Services, 2014

2013
Adaptive error correction in Orthogonal Latin Square Codes for low-power, resilient on-chip interconnection network.
Microelectron. Reliab., 2013

Reducing cache and TLB power by exploiting memory region and privilege level semantics.
J. Syst. Archit., 2013

Deadlock-free XY-YX router for on-chip interconnection network.
IEICE Electron. Express, 2013

A click model for time-sensitive queries.
Proceedings of the 22nd International World Wide Web Conference, 2013

mrGlove: FPGA-Based Data Glove for Heterogeneous Devices.
Proceedings of the Advanced Technologies, Embedded and Multimedia for Human-centric Computing, 2013

Intra-Body Communication for Personal Area Network.
Proceedings of the Advanced Technologies, Embedded and Multimedia for Human-centric Computing, 2013

In-Time Transaction Accelerator Architecture for RDBMS.
Proceedings of the Advanced Technologies, Embedded and Multimedia for Human-centric Computing, 2013

2012
Reducing L1 caches power by exploiting software semantics.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Evaluation of CUDA for X-Ray Imaging System.
Proceedings of the Computational Intelligence and Intelligent Systems, 2012

Single Photon Counting X-Ray Imaging System.
Proceedings of the Computational Intelligence and Intelligent Systems, 2012

Ambulatory Pattern Extraction for U-Health Care.
Proceedings of the Computational Intelligence and Intelligent Systems, 2012

Efficient Arctangent Computation for Real-Time Histograms of Oriented Gradients Descriptor Extraction.
Proceedings of the Computational Intelligence and Intelligent Systems, 2012

2011
CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition.
IEEE Micro, 2011

Area and power-efficient innovative congestion-aware Network-on-Chip architecture.
J. Syst. Archit., 2011

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs.
J. Parallel Distributed Comput., 2011

Low-Power, Resilient Interconnection with Orthogonal Latin Squares.
IEEE Des. Test Comput., 2011

Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

Opportunity of Accelerating User eXperience (UX) Technologies on Embedded Systems.
Proceedings of the Entertainment Computing - ICEC 2011 - 10th International Conference, 2011

Cost-effectively offering private buffers in SoCs and CMPs.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms.
Proceedings of the 48th Design Automation Conference, 2011

Cycle Accurate Power and Performance Simulator for Design Space Exploration on a Many-Core Platform.
Proceedings of the Advances in Computer Science, Environment, Ecoinformatics, and Education, 2011

Sharing Computation Resources in Image and Speech Recognition for Embedded Systems.
Proceedings of the Advances in Computer Science, Environment, Ecoinformatics, and Education, 2011

2010
Parallel processing for block ciphers on a fault tolerant networked processor array.
Int. J. High Perform. Syst. Archit., 2010

Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact.
IEEE Comput. Archit. Lett., 2010

Area and Power-efficient Innovative Network-on-Chip Architecurte.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

2009
A variable frequency link for a power-aware network-on-chip (NoC).
Integr., 2009

A high level power model for Network-on-Chip (NoC) router.
Comput. Electr. Eng., 2009

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

Low power adaptive pipeline based on instruction isolation.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Accelerating mobile augmented reality on a handheld platform.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture.
Parallel Process. Lett., 2008

A Generic Network Interface Architecture for a Networked Processor Array (NePA).
Proceedings of the Architecture of Computing Systems, 2008

2007
Design of a router for network-on-chip.
Int. J. High Perform. Syst. Archit., 2007

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

K-menu: a keyword-based dynamic menu interface for small computers.
Proceedings of the Extended Abstracts Proceedings of the 2007 Conference on Human Factors in Computing Systems, 2007

2006
Increasing the throughput of an adaptive router in network-on-chip (NoC).
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Photonic quantum corral, carrier ordering, and photonic quantum dot/ring device.
Microelectron. J., 2005

A simplified hand gesture interface for spherical manipulation in virtual environments.
Proceedings of the 2005 international conference on Augmented tele-existence, 2005


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