Seuk Son

Orcid: 0000-0003-4141-9425

Affiliations:
  • Seoul National University, Gwanak-gu, South Korea


According to our database1, Seuk Son authored at least 8 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2021
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery.
IEEE J. Solid State Circuits, 2019

2016
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function.
IEEE J. Solid State Circuits, 2014

2013
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.
IEEE J. Solid State Circuits, 2013

2012
Design of low-power high-radix switch fabric with partially-activated input and output lines.
Proceedings of the International SoC Design Conference, 2012

A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


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