Servando Espejo-Meana

Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2013

An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs.

[BibT_eX]

[DOI]

Samuel Sordo Ibáñez

Blanca Piñero-García

José Miguel Mora-Gutierrez

Antonio Ragel-Morales

Joaquin Ceballos Caceres

Manuel Munoz-Diaz

Luis Carranza-González

Alberto Arias-Drake

Miguel Ángel Lagos-Florido

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2009

New Visual Sensors and Processors.

[BibT_eX]

[DOI]

Luis Alba

Sergio Morillas-Castillo

Proceedings of the Spatial Temporal Patterns for Action-Oriented Perception in Roving Robots, 2009

2007

Data Matrix Code Recognition Using the Eye-RIS Vision System.

[BibT_eX]

[DOI]

Amanda Jimenez-Marrufo

Ainhoa Mendizabal

Sergio Morillas-Castillo

Rafael Romay-Juarez

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2004

ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs.

[BibT_eX]

[DOI]

L. Carranza

Elisenda Roca Moreno

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS.

[BibT_eX]

[DOI]

Carlos M. Domínguez-Matas

István Petrás

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

2003

A bio-inspired two-layer mixed-signal flexible programmable chip for early vision.

[BibT_eX]

[DOI]

Tamás Roska

Csaba Rekeczky

István Petrás

IEEE Trans. Neural Networks, 2003

An Improved Elementary Processing Unit For High-Density CNN-Based Mixed-Signal Microprocessors For Vision.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2003

ACE16k: A 128x128 Focal Plane Analog Processor with Digital I/O.

[BibT_eX]

[DOI]

Int. J. Neural Syst., 2003

CMOS Realization of a 2-Layer CNN Universal Machine Chip.

[BibT_eX]

[DOI]

Int. J. Neural Syst., 2003

Analog weight buffering strategy for CNN chips.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1000FPS@128×128 vision processor with 8-bit digitized I/O.

[BibT_eX]

[DOI]

Rafael Castro-López

Proceedings of the ESSCIRC 2003, 2003

2002

ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2002

Retinal Processing Emulation in a Programmable 2-Layer Analog Array Processor CMOS Chip.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 15 [Neural Information Processing Systems, 2002

Mismatch-induced tradeoffs and scalability of mixed-signal vision chips.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A processing element architecture for high-density focal plane analog programmable array processors.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

CMOS design of focal plane programmable array processors.

[BibT_eX]

[DOI]

Proceedings of the 9th European Symposium on Artificial Neural Networks, 2001

2000

Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips.

[BibT_eX]

[DOI]

Elisenda Roca

Manuel Delgado-Restituto

J. VLSI Signal Process., 1999

A Programmable Imager for Very High Speed Cellular Signal Processing.

[BibT_eX]

[DOI]

Elisenda Roca

J. VLSI Signal Process., 1999

An 0.5-µm CMOS Analog Random Access Memory Chip for TeraOPS Speed Multimedia Video Processing.

[BibT_eX]

[DOI]

Tamás Roska

Tibor Kozek

Leon O. Chua

IEEE Trans. Multim., 1999

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips.

[BibT_eX]

[DOI]

Ignacio Garcia-Vargas

Int. J. Circuit Theory Appl., 1999

1998

Electrooptical measurement system for the DC characterization of visible detectors for CMOS-compatible vision chips.

[BibT_eX]

[DOI]

Elisenda Roca

Fabián Frutos

IEEE Trans. Instrum. Meas., 1998

A 64×64 CNN universal chip with analog and digital I/O.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997

A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

1996

A VLSI-oriented continuous-time CNN model.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1996

A CNN Universal Chip in CMOS Technology.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1996

1995

Realization of a CNN Universal Chip in CMOS Technolgy.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Smart-pixel cellular neural networks in analog current-mode CMOS technology.

[BibT_eX]

[DOI]

John L. Huertas

Edgar Sánchez-Sinencio

IEEE J. Solid State Circuits, August, 1994

1993

A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques.

[BibT_eX]