Serhiy Avramenko
Orcid: 0000-0001-5698-8327Affiliations:
- Polytechnic University of Turin, Italy
According to our database1,
Serhiy Avramenko
authored at least 12 papers
between 2015 and 2019.
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Bibliography
2019
Network-on-Chip-based Multi-Processor System-on-Chip: Towards Mixed-Criticality System Certification.
PhD thesis, 2019
J. Electron. Test., 2019
2018
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
2017
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.
J. Electron. Test., 2017
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables.
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2015
An Hybrid Architecture for consolidating mixed criticality applications on multicore systems.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015