Sergi Vilardell

According to our database, Sergi Vilardell authored at least 7 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Event Monitor Validation in High-Integrity Systems.

Roger Pujol, Sergi Vilardell, Enrico Mezzetti, Mohamed Hassan, Jaume Abella, Francisco J. Cazorla

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023

Modelling and predicting extreme behavior in critical real-time systems with advanced statistics

Sergi Vilardell

PhD thesis, 2023

2022

Using Markov's Inequality with Power-Of-k Function for Probabilistic WCET Estimation.

Sergi Vilardell, Isabel Serra, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, Joan del Castillo

Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

2021

MUCH: exploiting pairwise hardware event monitor correlations for improved timing analysis of complex MPSoCs.

Sergi Vilardell, Isabel Serra, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla

Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

2020

HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs.

Sergi Vilardell, Isabel Serra, Roberto Santalla, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CleanET: enabling timing validation for complex automotive systems.

Sergi Vilardell, Isabel Serra, Hamid Tabani, Jaume Abella, Joan del Castillo, Francisco J. Cazorla

Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

2019

Software Timing Analysis for Complex Hardware with Survivability and Risk Analysis.

Sergi Vilardell, Isabel Serra, Jaume Abella, Joan del Castillo, Francisco J. Cazorla

Proceedings of the 37th IEEE International Conference on Computer Design, 2019