Sergey Ostanin

According to our database, Sergey Ostanin authored at least 28 papers between 2000 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Masking Robust Testable PDFs.

Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

2018

Finding False Paths for Sequential Circuits Using Operations on ROBDDs.

Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults.

Sergey Ostanin, Valentina Andreeva, Natalia Butorina, D. Tretyakov

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Trojan circuits masking and debugging of combinational circuits with LUT insertion.

Anzhela Yu. Matrosova, Sergey Ostanin

Proceedings of the IEEE International Conference on Automation, 2018

2017

Trojan circuits preventing and masking in sequential circuits.

Anjela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Self-checking synchronous FSM network design for path delay faults.

Sergey Ostanin

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Logic circuit design with gates, LUTs and MUXs oriented to mask faults.

Anzhela Yu. Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Detection and masking of Trojan Circuits in sequential logic.

Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergey Ostanin, Ekaterina Nikolaeva

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Preventing and masking Trojan circuits triggering out of working area.

Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016

A fault-tolerant sequential circuit design for SAFs and PDFs soft errors.

Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit.

Sergey Ostanin, Anzhela Yu. Matrosova, Natalia Butorina, V. Lavrov

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Patching circuit design based on reserved CLBs.

Anjela Yu. Matrosova, Sergey Ostanin, Valentina Andreeva

Proceedings of the IEEE International Conference on Automation, 2016

2015

A fault-tolerant combinational circuit design.

Sergey Ostanin, Irina Kirienko, V. Lavrov

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Fault-tolerant high performance scheme design.

Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit.

Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Partially programmable circuit design.

Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh

Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013

Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs.

Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh

Autom. Remote. Control., 2013

Testable combinational circuit design based on free ZDD-implementation of irredundant SOPof Boolean function.

Sergey Ostanin

Proceedings of the East-West Design & Test Symposium, 2013

Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques.

Anzhela Yu. Matrosova, Sergey Ostanin, Alexey Melnikov, Virendra Singh

Proceedings of the East-West Design & Test Symposium, 2013

2011

Implementation by the special formula of an arbitrary subset of code words of (m, n)-code for designing a self-testing checker.

Natalia Butorina, Sergey Ostanin

Proceedings of the 9th East-West Design & Test Symposium, 2011

2010

Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function.

Sergey Ostanin, R. Muchamedov

Proceedings of the 2010 East-West Design & Test Symposium, 2010

2007

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs.

Anjela Yu. Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikolaeva

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2002

Sequential Circuits Applicable for Detecting Different Types of Faults.

Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky, Sergey Ostanin

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Self-checking sequential circuits with self-healing ability.

Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Fault Latencies of Concurrent Checking FSMs.

Roman Goot, Ilya Levin, Sergei Ostanin

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

Survivable Self-Checking Sequential Circuits.

Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000

Self-checking Synchronous FSM Network Design with Low Overhead.

Anzhela Yu. Matrosova, Ilya Levin, Sergey Ostanin

VLSI Design, 2000

Self-Checking FSM Design with Observing only FSM Outputs.

Anzhela Yu. Matrosova, Sergey Ostanin

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000