Sergej Deutsch

According to our database1, Sergej Deutsch authored at least 26 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Cryptographic Capability Computing.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
Κ-Cipher: A Low Latency, Bit Length Parameterizable Cipher.
IACR Cryptol. ePrint Arch., 2020

The MAGIC Mode for Simultaneously Supporting Encryption, Message Authentication and Error Correction.
IACR Cryptol. ePrint Arch., 2020

Gimli Encryption in 715.9 psec.
IACR Cryptol. ePrint Arch., 2020

Security definitions, entropy measures and constructions for implicitly detecting data corruption.
Comput. Commun., 2020

K-Cipher: A Low Latency, Bit Length Parameterizable Cipher.
Proceedings of the IEEE Symposium on Computers and Communications, 2020

2019
IVP: A Three Level Confusion-Diffusion Network Supporting Implicit Data Integrity.
Proceedings of the 2019 IEEE Symposium on Computers and Communications, 2019

2018
Cryptographic Constructions Supporting Implicit Data Integrity.
IACR Cryptol. ePrint Arch., 2018

Implicit Data Integrity: Protecting User Data without MACs.
Proceedings of the 15th International Joint Conference on e-Business and Telecommunications, 2018

There is No Need to Waste Communication Bandwidth on MACs.
Proceedings of the 2018 Global Information Infrastructure and Networking Symposium, 2018

2017
Non-recursive computation of the probability of more than two people having the same birthday.
Proceedings of the 2017 IEEE Symposium on Computers and Communications, 2017

2016
The hype, myths, and realities of testing 3D integrated circuits.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Robust Optimization of Test-Access Architectures Under Realistic Scenarios.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Test and debug solutions for 3D-stacked integrated circuits.
Proceedings of the 2015 IEEE International Test Conference, 2015

Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators.
Proceedings of the 2015 IEEE International Test Conference, 2015

Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Test and Design-for-Testability Solutions for 3D Integrated Circuits.
IPSJ Trans. Syst. LSI Des. Methodol., 2014

Vesuvius-3D: A 3D-DfT demonstrator.
Proceedings of the 2014 International Test Conference, 2014

Massive signal tracing using on-chip DRAM for in-system silicon debug.
Proceedings of the 2014 International Test Conference, 2014

2013
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs.
Proceedings of the 2013 IEEE International Test Conference, 2013

Robust optimization of test-architecture designs for core-based SoCs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.
Proceedings of the 2012 IEEE International Test Conference, 2012

TSV Stress-Aware ATPG for 3D Stacked ICs.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Automation of 3D-DfT Insertion.
Proceedings of the 20th IEEE Asian Test Symposium, 2011


  Loading...