Sergej Deutsch
According to our database1,
Sergej Deutsch
authored at least 26 papers
between 2011 and 2021.
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Bibliography
2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
2020
IACR Cryptol. ePrint Arch., 2020
The MAGIC Mode for Simultaneously Supporting Encryption, Message Authentication and Error Correction.
IACR Cryptol. ePrint Arch., 2020
Security definitions, entropy measures and constructions for implicitly detecting data corruption.
Comput. Commun., 2020
Proceedings of the IEEE Symposium on Computers and Communications, 2020
2019
Proceedings of the 2019 IEEE Symposium on Computers and Communications, 2019
2018
IACR Cryptol. ePrint Arch., 2018
Proceedings of the 15th International Joint Conference on e-Business and Telecommunications, 2018
Proceedings of the 2018 Global Information Infrastructure and Networking Symposium, 2018
2017
Non-recursive computation of the probability of more than two people having the same birthday.
Proceedings of the 2017 IEEE Symposium on Computers and Communications, 2017
2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators.
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 International Test Conference, 2014
2013
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011