Sergei Y. Larin

According to our database, Sergei Y. Larin authored at least 3 papers between 1996 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors.

Sergei Y. Larin, Thomas M. Conte

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

1998

Value Speculation Scheduling for High Performance Processors.

Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte

Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1996

Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.

Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996