Serge Weber
Orcid: 0000-0002-7851-9916
According to our database1,
Serge Weber
authored at least 49 papers
between 1996 and 2023.
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Bibliography
2023
Eng. Appl. Artif. Intell., 2023
2022
IEEE Trans. Aerosp. Electron. Syst., 2022
2020
Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantization.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the IECON 2019, 2019
2018
Microprocess. Microsystems, 2018
High performance scalable hardware SOM architecture for real-time vector quantization.
Proceedings of the IEEE International Conference on Image Processing, 2018
2016
Proceedings of the Advances in Self-Organizing Maps and Learning Vector Quantization, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2014
A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores.
IEEE Embed. Syst. Lett., 2014
2013
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM.
Microprocess. Microsystems, 2013
Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
An approach: FPGA based dynamically reconfigurable architecture to enable several scheme controls for power converters.
Proceedings of the 9th International Conference on Electrical Engineering, 2012
2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Efficient reconfigurable entropy coder for embedded multi-standards video adaptation.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011
2009
An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis.
IEEE Trans. Circuits Syst. Video Technol., 2009
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs.
Microprocess. Microsystems, 2009
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation.
J. Univers. Comput. Sci., 2007
A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the FPL 2007, 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performance.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable system.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.
Proceedings of the Field Programmable Logic and Application, 2004
FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
Linear array processors with multiple access modes memory for real-time image processing.
Real Time Imaging, 2003
Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system.
Microprocess. Microsystems, 2003
A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems.
EURASIP J. Adv. Signal Process., 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Linear array processors with multiple access modes memory for real-time image processing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2000
Proceedings of the Parallel and Distributed Processing, 2000
1999
SIMD/restricted MIMD parallel architecture for Image Processing Based on a New Design of a Multi-mode Access Memory.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999
1996
LAPCAM, Linear Array of Processors Using Content-Addressable Memories: A New Design of Machine Vision for Parallel Image Computations.
Proceedings of IAPR Workshop on Machine Vision Applications, 1996
Proceedings of the 13th International Conference on Pattern Recognition, 1996