Serdar Tasiran

According to our database1, Serdar Tasiran authored at least 65 papers between 1994 and 2021.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of three.

Timeline

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Links

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Bibliography

2021
Code-level model checking in the software development workflow at Amazon Web Services.
Softw. Pract. Exp., 2021

Model checking boot code from AWS data centers.
Formal Methods Syst. Des., 2021

Using Lightweight Formal Methods to Validate a Key-Value Storage Node in Amazon S3.
Proceedings of the SOSP '21: ACM SIGOPS 28th Symposium on Operating Systems Principles, 2021

2020
Continuous Compliance.
Proceedings of the 35th IEEE/ACM International Conference on Automated Software Engineering, 2020

Code-level model checking in the software development workflow.
Proceedings of the ICSE-SEIP 2020: 42nd International Conference on Software Engineering, Software Engineering in Practice, Seoul, South Korea, 27 June, 2020

2019
A Machine-Checked Proof of Security for AWS Key Management Service.
IACR Cryptol. ePrint Arch., 2019

A mechanized refinement proof of the Chase-Lev deque using a proof system.
Computing, 2019

2018
Output nondeterminism detection for programming models combining dataflow with shared memory.
Parallel Comput., 2018

Practical Methods for Reasoning About Java 8's Functional Programming Features.
Proceedings of the Verified Software. Theories, Tools, and Experiments, 2018

SideTrail: Verifying Time-Balancing of Cryptosystems.
Proceedings of the Verified Software. Theories, Tools, and Experiments, 2018

Continuous Formal Verification of Amazon s2n.
Proceedings of the Computer Aided Verification - 30th International Conference, 2018

Reasoning About TSO Programs Using Reduction and Abstraction.
Proceedings of the Computer Aided Verification - 30th International Conference, 2018

2017
Consistency-Aware Scheduling for Weakly Consistent Programs.
ACM SIGSOFT Softw. Eng. Notes, 2017

A solver-aided language for test input generation.
Proc. ACM Program. Lang., 2017

EmbedSanitizer: Runtime Race Detection Tool for 32-bit Embedded ARM.
Proceedings of the Runtime Verification - 17th International Conference, 2017

Verifying Robustness of Event-Driven Asynchronous Programs Against Concurrency.
Proceedings of the Programming Languages and Systems, 2017

2015
TRADE: Precise Dynamic Race Detection for Scalable Transactional Memory Systems.
ACM Trans. Parallel Comput., 2015

Moving Around: Lipton's Reduction for TSO - (Regular Submission).
Proceedings of the Verified Software: Theories, Tools, and Experiments, 2015

Detecting JavaScript races that matter.
Proceedings of the 2015 10th Joint Meeting on Foundations of Software Engineering, 2015

Verification Tools for Transactional Programs.
Proceedings of the Transactional Memory. Foundations, Algorithms, Tools, and Applications, 2015

Systematic Asynchrony Bug Exploration for Android Apps.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

Automated and Modular Refinement Reasoning for Concurrent Programs.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014
Exploiting synchronization in the analysis of shared-memory asynchronous programs.
Proceedings of the 2014 International Symposium on Model Checking of Software, 2014

Dynamic Verification for Hybrid Concurrent Programming Models.
Proceedings of the Runtime Verification - 5th International Conference, 2014

I Know It When I See It: Observable Races in JavaScript Applications.
Proceedings of the Workshop on Dynamic Languages and Applications, 2014

Towards verifying eventually consistent applications.
Proceedings of the First Workshop on the Principles and Practice of Eventual Consistency, 2014

T-Rex: a dynamic race detection tool for C/C++ transactional memory applications.
Proceedings of the Ninth Eurosys Conference 2014, 2014

2012
Runtime verification of concurrency-specific correctness criteria.
Int. J. Softw. Tools Technol. Transf., 2012

Location pairs: a test coverage metric for shared-memory concurrent programs.
Empir. Softw. Eng., 2012

2010
Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Editorial.
J. Log. Comput., 2010

Goldilocks: a race-aware Java runtime.
Commun. ACM, 2010

Tressa: Claiming the Future.
Proceedings of the Verified Software: Theories, 2010

Simplifying Linearizability Proofs with Reduction and Abstraction.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2010

Run-Time Verification of Optimistic Concurrency.
Proceedings of the Runtime Verification - First International Conference, 2010

2009
A calculus of atomic actions.
Proceedings of the 36th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2009

An annotation assistant for interactive debugging of programs with common synchronization idioms.
Proceedings of the 7th Workshop on Parallel and Distributed Systems: Testing, 2009

Verifying Optimistic Concurrency: Prophecy Variables and Backward Reasoning.
Proceedings of the Design and Validation of Concurrent Systems, 30.08. - 04.09.2009, 2009

2008
Using Haptics to Convey Cause-and-Effect Relations in Climate Visualization.
IEEE Trans. Haptics, 2008

Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE)
CoRR, 2008

2007
Rollback Atomicity.
Proceedings of the Runtime Verification, 7th International Workshop, 2007

Goldilocks: a race and transaction-aware java runtime.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

2006
A classification of concurrency bugs in java benchmarks by developer intent.
Proceedings of the 4th Workshop on Parallel and Distributed Systems: Testing, 2006

Goldilocks: Efficiently Computing the Happens-Before Relation Using Locksets.
Proceedings of the Formal Approaches to Software Testing and Runtime Verification, 2006

2005
VyrdMC: Driving Runtime Refinement Checking with Model Checkers.
Proceedings of the Fifth Workshop on Runtime Verification, 2005

VYRD: verifYing concurrent programs by runtime refinement-violation detection.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

A Novel Test Coverage Metric for Concurrently-Accessed Software Components.
Proceedings of the Formal Approaches to Software Testing, 5th International Workshop, 2005

Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

2004
Runtime Refinement Checking of Concurrent Data Structures.
Proceedings of the Fourth Workshop on Runtime Verification, 2004

Linking Simulation with Formal Verification at a Higher Level.
IEEE Des. Test Comput., 2004

2003
TreeJuxtaposer: scalable tree comparison using Focus+Context with guaranteed visibility.
ACM Trans. Graph., 2003

Checking Cache-Coherence Protocols with TLA<sup>+</sup>.
Formal Methods Syst. Des., 2003

Using a formal specification and a model checker to monitor and direct simulation.
Proceedings of the 40th Design Automation Conference, 2003

2002
An assume-guarantee rule for checking simulation.
ACM Trans. Program. Lang. Syst., 2002

Promising Directions in Hardware Design Verification (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001
Coverage Metrics for Functional Validation of Hardware Designs.
IEEE Des. Test Comput., 2001

A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1999
Formal verification meets simulation (tutorial abstract).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
MOCHA: Modularity in Model Checking.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997
STARI: A Case Study in Compositional and Hierarchical Timing Verification.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

1996
Verifying Abstractions of Timed Systems.
Proceedings of the CONCUR '96, 1996

1995
Language containment of non-deterministic <i>omega</i>-automata.
Proceedings of the Correct Hardware Design and Verification Methods, 1995

1994
BDD Variable Ordering for Interacting Finite State Machines.
Proceedings of the 31st Conference on Design Automation, 1994

HSIS: A BDD-Based Environment for Formal Verification.
Proceedings of the 31st Conference on Design Automation, 1994


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