Serdar Süer Erdem

Orcid: 0000-0002-9637-583X

According to our database1, Serdar Süer Erdem authored at least 9 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2019
A High Performance Full-Word Barrett Multiplier Designed for FPGAs with DSP Resources.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018
A fast digit based Montgomery multiplier designed for FPGAs with DSP resources.
Microprocess. Microsystems, 2018

2017
A General Digit-Serial Architecture for Montgomery Modular Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2015
Versatile digit serial multipliers for binary extension fields.
Comput. Electr. Eng., 2015

2014
On Selection of Modulus of Quadratic Codes for the Protection of Cryptographic Operations against Fault Attacks.
IEEE Trans. Computers, 2014

2011
On Protecting Cryptographic Applications Against Fault Attacks Using Residue Codes.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

2010
Design and implementation of robust embedded processor for cryptographic applications.
Proceedings of the 3rd International Conference on Security of Information and Networks, 2010

2009
Fast Finite Field Multiplication.
Proceedings of the Cryptographic Engineering, 2009

2003
A Less Recursive Variant of Karatsuba-Ofman Algorithm for Multiplying Operands of Size a Power of Two.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003


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