Serdar A. Yonar

According to our database, Serdar A. Yonar authored at least 3 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform.

Jaewon Lee, Seoyoung Jang, Yujin Choi, Donggeon Kim, Serdar A. Yonar, Matthias Braendli, Andrea Ruffino, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

2023

An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches.

Serdar A. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Mridula Prathapan, Thomas Morf, Andrea Ruffino, Taekwang Jang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS.

Marcel A. Kossel, Vishal Khatri, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Serdar A. Yonar, Mridula Prathapan, Eric J. Lukes, Raymond A. Richetta, Carrie Cox

Proceedings of the IEEE International Solid-State Circuits Conference, 2021