Septafiansyah Dwi Putra

Orcid: 0000-0001-8669-1217

According to our database1, Septafiansyah Dwi Putra authored at least 5 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features.
IEEE Access, 2023

2021
Efficient Machine Learning Model for Hardware Trojan Detection on Register Transfer Level.
Proceedings of the 4th International Conference on Signal Processing and Information Security, 2021

Power Analysis in Hamming Weight Model: Attacking IoT Encryption Devices.
Proceedings of the 4th International Conference on Signal Processing and Information Security, 2021

2018
Design of an AES Device as Device Under Test in a DPA Attack.
Int. J. Netw. Secur., 2018

Attacking AES-Masking Encryption Device with Correlation Power Analysis.
Int. J. Commun. Networks Inf. Secur., 2018


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