Septafiansyah Dwi Putra
Orcid: 0000-0001-8669-1217
According to our database1,
Septafiansyah Dwi Putra
authored at least 5 papers
between 2018 and 2023.
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Bibliography
2023
Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features.
IEEE Access, 2023
2021
Efficient Machine Learning Model for Hardware Trojan Detection on Register Transfer Level.
Proceedings of the 4th International Conference on Signal Processing and Information Security, 2021
Proceedings of the 4th International Conference on Signal Processing and Information Security, 2021
2018
Int. J. Netw. Secur., 2018
Int. J. Commun. Networks Inf. Secur., 2018