Sepehr Tabrizchi
Orcid: 0000-0001-5105-3450
According to our database1,
Sepehr Tabrizchi
authored at least 38 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
IEEE Trans. Emerg. Top. Comput., 2024
HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.
CoRR, 2024
DECO: Dynamic Energy-aware Compression and Optimization for In-Memory Neural Networks.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Resource-Efficient Adaptive-Network Inference Framework with Knowledge Distillation-Based Unified Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
IEEE Trans. Emerg. Top. Comput., 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Conference on Rebooting Computing, 2023
EnCoDe: Enhancing Compressed Deep Learning Models Through Feature - - - Distillation and Informative Sample Selection.
Proceedings of the International Conference on Machine Learning and Applications, 2023
SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
CoRR, 2022
IEEE Comput. Archit. Lett., 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
SCiMA: A Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
Circuits Syst. Signal Process., 2021
2020
Microelectron. J., 2020
Designing positive, negative and standard gates for ternary logics using quantum dot cellular automata.
Comput. Electr. Eng., 2020
2019
An energy-based heterogeneity measure for quantifying structural irregularity in complex networks.
J. Comput. Sci., 2019
Novel CNFET ternary circuit techniques for high-performance and energy-efficient design.
IET Circuits Devices Syst., 2019
High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design.
Comput. Electr. Eng., 2019
2018
2017
A novel ternary half adder and multiplier based on carbon nanotube field effect transistors.
Frontiers Inf. Technol. Electron. Eng., 2017
IET Circuits Devices Syst., 2017
2016
Circuits Syst. Signal Process., 2016