Sepehr Tabrizchi

Orcid: 0000-0001-5105-3450

According to our database1, Sepehr Tabrizchi authored at least 38 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks.
IEEE Trans. Emerg. Top. Comput., 2024

HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.
CoRR, 2024

DECO: Dynamic Energy-aware Compression and Optimization for In-Memory Neural Networks.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

ResSen: Imager Privacy Enhancement Through Residue Arithmetic Processing in Sensors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Energy-Efficient Near-Sensor Event Detector Based on Multilevel Ga2O3 RRAM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Resource-Efficient Adaptive-Network Inference Framework with Knowledge Distillation-Based Unified Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems.
IEEE Trans. Emerg. Top. Comput., 2023

Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

NeSe: Near-Sensor Event-Driven Scheme for Low Power Energy Harvesting Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Deep Mapper: A Multi-Channel Single-Cycle Near-Sensor DNN Accelerator.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023

EnCoDe: Enhancing Compressed Deep Learning Models Through Feature - - - Distillation and Informative Sample Selection.
Proceedings of the International Conference on Machine Learning and Applications, 2023

SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

P-PIM: A Parallel Processing-in-DRAM Framework Enabling Row Hammer Protection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
PISA: A Binary-Weight Processing-In-Sensor Accelerator for Edge Image Processing.
CoRR, 2022

LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking.
IEEE Comput. Archit. Lett., 2022

Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

SCiMA: A Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell.
Circuits Syst. Signal Process., 2021

2020
A novel method for reduction partial product tree in ternary multiplier.
Microelectron. J., 2020

Designing positive, negative and standard gates for ternary logics using quantum dot cellular automata.
Comput. Electr. Eng., 2020

2019
An energy-based heterogeneity measure for quantifying structural irregularity in complex networks.
J. Comput. Sci., 2019

Novel CNFET ternary circuit techniques for high-performance and energy-efficient design.
IET Circuits Devices Syst., 2019

High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design.
Comput. Electr. Eng., 2019

2018
Energy Efficient Tri-State CNFET Ternary Logic Gates.
CoRR, 2018

2017
A novel ternary half adder and multiplier based on carbon nanotube field effect transistors.
Frontiers Inf. Technol. Electron. Eng., 2017

Method for designing ternary adder cells based on CNFETs.
IET Circuits Devices Syst., 2017

2016
A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs.
Circuits Syst. Signal Process., 2016


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