Seoyoung Jang
Orcid: 0009-0008-1056-0470
According to our database1,
Seoyoung Jang
authored at least 9 papers
in 2024.
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Bibliography
2024
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links.
Proceedings of the 21st International SoC Design Conference, 2024
A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links.
Proceedings of the 21st International SoC Design Conference, 2024
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024