Seongmoon Wang

According to our database1, Seongmoon Wang authored at least 38 papers between 1997 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
An efficient method to screen resistive opens under presence of process variation.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
A Low Overhead High Test Compression Technique Using Pattern Clustering With $n$-Detection Test Support.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips.
IEEE Trans. Computers, 2010

2009
Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A self-diagnosis technique using Reed-Solomon codes for self-repairing chips.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

Machine learning-based volume diagnosis.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors.
IEEE Trans. Computers, 2008

Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns.
Proceedings of the 13th European Test Symposium, 2008

Cost Efficient Methods to Improve Performance of Broadcast Scan.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A BIST TPG for Low Power Dissipation and High Fault Coverage.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Zero Cost Test Point Insertion Technique for Structured ASICs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A low cost test data compression technique for high n-detection fault coverage.
Proceedings of the 2007 IEEE International Test Conference, 2007

A hybrid scheme for compacting test responses with unknown values.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Unknown blocking scheme for low control data volume and high observability.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding.
Proceedings of the 16th Asian Test Symposium, 2007

A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
LT-RTPG: a new test-per-scan BIST TPG for low switching activity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

PIDISC: Pattern Independent Design Independent Seed Compression Technique.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Efficient unknown blocking using LFSR reseeding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Coverage loss by using space compactors in presence of unknown values.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.
Proceedings of the 43rd Design Automation Conference, 2006

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

XWRC: externally-loaded weighted random pattern testing for input test data compression.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Response shaper: a novel technique to enhance unknown tolerance for output response compaction.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets.
Proceedings of the 2004 Design, 2004

Re-configurable embedded core test protocol.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002
An automatic test pattern generator for minimizing switching activity during scan testing activity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

DS-LFSR: a BIST TPG for low switching activity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999
LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
ATPG for Heat Dissipation Minimization During Test Application.
IEEE Trans. Computers, 1998

1997
DS-LFSR: A New BIST TPG for Low Heat Dissipation.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

ATPG for Heat Dissipation Minimization During Scan Testing.
Proceedings of the 34st Conference on Design Automation, 1997


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