Seongmoon Wang
According to our database1,
Seongmoon Wang
authored at least 38 papers
between 1997 and 2011.
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Bibliography
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
2010
A Low Overhead High Test Compression Technique Using Pattern Clustering With $n$-Detection Test Support.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips.
IEEE Trans. Computers, 2010
2009
Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors.
IEEE Trans. Computers, 2008
Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns.
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding.
Proceedings of the 16th Asian Test Symposium, 2007
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.
Proceedings of the 43rd Design Automation Conference, 2006
Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs.
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
XWRC: externally-loaded weighted random pattern testing for input test data compression.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Response shaper: a novel technique to enhance unknown tolerance for output response compaction.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
2004
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2002
An automatic test pattern generator for minimizing switching activity during scan testing activity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
IEEE Trans. Computers, 1998
1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the 34st Conference on Design Automation, 1997