Seongmin Hong

Orcid: 0000-0002-4723-4547

According to our database1, Seongmin Hong authored at least 17 papers between 2017 and 2024.

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Bibliography

2024
Gradient-free Decoder Inversion in Latent Diffusion Models.
CoRR, 2024

Adaptive Selection of Sampling-Reconstruction in Fourier Compressed Sensing.
CoRR, 2024

LPU: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference.
CoRR, 2024

Adaptive Selection of Sampling-Reconstruction in Fourier Compressed Sensing.
Proceedings of the Computer Vision - ECCV 2024, 2024

On Exact Inversion of DPM-Solvers.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

2023
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

On the Robustness of Normalizing Flows for Inverse Problems in Imaging.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

HyperAccel Latency Processing Unit (LPU<sup>TM</sup>) Accelerating Hyperscale Models for Generative AI.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

Neural Diffeomorphic Non-uniform B-spline Flows.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support.
IEEE Trans. Very Large Scale Integr. Syst., 2022

DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text Generation.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022



2021
FIXAR: A Fixed-Point Deep Reinforcement Learning Platform with Quantization-Aware Training and Adaptive Parallelism.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2018
Automated Neural Network Accelerator Generation Framework for Multiple Neural Network Applications.
Proceedings of the TENCON 2018, 2018

NN compactor: Minimizing memory and logic resources for small neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A FPGA-based neural accelerator for small IoT devices.
Proceedings of the International SoC Design Conference, 2017


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