Seong-Young Seo

According to our database, Seong-Young Seo authored at least 7 papers between 2009 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.

Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Hyunui Lee, Seok-Yong Kang, Young-Soo Sohn, Jung-Hwan Choi, Yong-Cheol Bae, Seong-Jin Jang, Gyo-Young Jin

IEEE J. Solid State Circuits, 2017

2016

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.

Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013

An all-digital PLL with supply insensitive digitally controlled oscillator.

Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Kee-Won Kwon

IEICE Electron. Express, 2013

2011

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity.

Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Seok Kim, Kee-Won Kwon

IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010

MS aided MBS enhancement algorithm.

Seong-Young Seo, Suk Chan Kim, Young Il Kim

Proceedings of the International Conference on Information and Communication Technology Convergence, 2010

3D image transmission technology for mobile IPTV.

Young-Il Kim, Gonchigsumlaa Khishigjargal, Soon Young Song, Yong Su Lee, Park Dae Geun, Chun Sun Sim, Park Young Soo, Yeonjoon Chung, Cheol-Hye Cho, Won Ryu, Seong-Young Seo, Suk Chan Kim, Naimannaran Chuluunbandi

Proceedings of the International Conference on Information and Communication Technology Convergence, 2010

2009

1.2V 1.6Gb/s 56nm 6F² 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.

Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim

Proceedings of the IEEE International Solid-State Circuits Conference, 2009