Seong-Ook Jung
Orcid: 0000-0003-0757-2581
According to our database1,
Seong-Ook Jung
authored at least 159 papers
between 2000 and 2024.
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Bibliography
2024
A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2024
Split WL 6T SRAM-Based Bit Serial Computing-in-Memory Macro With High Signal Margin and High Throughput.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A Charge-Domain 4T2C eDRAM Compute-in-Memory Macro With Enhanced Variation Tolerance and Low-Overhead Data Conversion Schemes.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A CNN-Based Super-Resolution Processor With Short-Term Caching for Real-Time UHD Upscaling.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
Design of Physically Unclonable Function Using Ferroelectric FET With Auto Write-Back Technique for Resource-Limited IoT Security.
IEEE Internet Things J., 2024
15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
IEEE J. Solid State Circuits, November, 2023
An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
IEEE Trans. Circuits Syst. II Express Briefs, 2023
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices.
IEEE J. Solid State Circuits, 2023
A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm<sup>2</sup> CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique.
IEEE Trans. Inf. Forensics Secur., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 6.9-μm<sup>2</sup> 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation.
IEEE J. Solid State Circuits, 2021
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation.
IEEE Access, 2021
Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells.
IEEE Access, 2021
IEEE Access, 2021
Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM.
IEEE Access, 2021
All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash.
IEEE Access, 2021
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit.
Proceedings of the 18th International SoC Design Conference, 2021
2020
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability.
IEEE Trans. Inf. Forensics Secur., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit.
Sensors, 2020
IEEE Access, 2020
IEEE Access, 2020
IEEE Access, 2020
A Read Voltage Modulation Technique for Leakage Current Compensation in Cross-Point OTS-PRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE J. Solid State Circuits, 2019
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
IEEE J. Solid State Circuits, 2019
2018
All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
0.293-mm<sup>2</sup> Fast Transient Response Hysteretic Quasi-V<sup>2</sup> DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS.
IEEE J. Solid State Circuits, 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic Synapse.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
Int. J. Circuit Theory Appl., 2017
2016
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator.
IEEE Trans. Very Large Scale Integr. Syst., 2016
An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm.
IEICE Electron. Express, 2016
Equalization scheme analysis for high-density spin transfer torque random access memory.
Proceedings of the International SoC Design Conference, 2016
WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management.
IEEE Trans. Very Large Scale Integr. Syst., 2015
SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Reference-circuit analysis for high-bandwidth spin transfer torque random access memory.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Int. J. Circuit Theory Appl., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Int. J. Circuit Theory Appl., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE International Conference on Consumer Electronics, 2013
All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate.
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Integration of dual channel timing formatter system for high speed memory test equipment.
Proceedings of the International SoC Design Conference, 2012
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.
Proceedings of the International SoC Design Conference, 2012
Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Int. J. Circuit Theory Appl., 2011
Proceedings of the International SoC Design Conference, 2011
2010
IEEE Trans. Consumer Electron., 2010
IEEE Trans. Consumer Electron., 2010
Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits.
IEICE Trans. Electron., 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
2007
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
2004
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. Very Large Scale Integr. Syst., 2003
ACM Trans. Design Autom. Electr. Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
2002
Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology
PhD thesis, 2002
Noise constrained transistor sizing and power optimization for dual Vs<sub>t</sub> domino logic.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Transistor sizing for reliable domino logic design in dual threshold voltage technologies.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
Proceedings of the 38th Design Automation Conference, 2001
2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000