Seon-Kyoo Lee
Orcid: 0009-0001-9349-8615
According to our database1,
Seon-Kyoo Lee
authored at least 22 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A $94\text{fs}_{\text{rms}}$-Jitter and -249.3dB FoM 4.0GHz Ring-Oscillator-Based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2021
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.
IEEE J. Solid State Circuits, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2016
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE J. Solid State Circuits, 2014
2013
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface.
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
J. Electr. Comput. Eng., 2011
2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009