Seokin Hong

Orcid: 0000-0001-7842-125X

According to our database1, Seokin Hong authored at least 36 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SAVector: Vectored Systolic Arrays.
IEEE Access, 2024

A Case for Speculative Address Translation with Rapid Validation for GPUs.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Distributed Page Table: Harnessing Physical Memory as an Unbounded Hashed Page Table.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Leveraging Algorithm-based Fault Tolerance for Propagation Error Detection in NPUs.
Proceedings of the 21st International SoC Design Conference, 2024

Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023
On the Positional Single Error Correction and Double Error Detection in Racetrack Memories.
IEEE Access, 2023

Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers.
Proceedings of the 20th International SoC Design Conference, 2023

Conveyor: Towards Asynchronous Dataflow in Systolic Array to Exploit Unstructured Sparsity.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Facto-CNN: Memory-Efficient CNN Training with Low-rank Tensor Factorization and Lossy Tensor Compression.
Proceedings of the Asian Conference on Machine Learning, 2023

SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
A Case Study of Quantizing Convolutional Neural Networks for Fast Disease Diagnosis on Portable Medical Devices.
Sensors, 2022

Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation.
IEEE Access, 2022

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches.
IEEE Access, 2022

On-the-Fly Lowering Engine: Offloading Data Layout Conversion for Convolutional Neural Networks.
IEEE Access, 2022

Don't open row: rethinking row buffer policy for improving performance of non-volatile memories.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems.
IEEE Trans. Computers, 2021

Proactive Dead Block Eviction for Reducing Write Latency in STT-MRAM Caches.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

2020
ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Split-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2017
CramSim: controller and memory simulator.
Proceedings of the International Symposium on Memory Systems, 2017

Partial Row Activation for Low-Power DRAM System.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures.
IEEE Trans. Computers, 2016

2015
Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho.
IEEE Trans. Computers, 2015

A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU.
IEEE Trans. Computers, 2015

2014
Ternary cache: Three-valued MLC STT-RAM caches.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Skinflint DRAM system: Minimizing DRAM chip writes for low power.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

AVICA: an access-time variation insensitive L1 cache architecture.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

TLB index-based tagging for cache energy reduction.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
TEPS: Transient Error Protection Utilizing Sub-word Parallelism.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2001
Rules of Convergence - What Would Become the Face of the Internet TV?
Proceedings of the Fifth Pacific Asia Conference on Information Systems, 2001


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