Seokhyeong Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space Optimization.

[BibT_eX]

[DOI]

Jaemin Seo

Sejin Park

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning.

[BibT_eX]

[DOI]

Sung-Yun Lee

Kyungjun Min

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

ViT- ToGo: Vision Transformer Accelerator with Grouped Token Pruning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Improvement of Mixed Track - Height Standard-Cell Placement.

[BibT_eX]

[DOI]

Minhyuk Kweon

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

HiLight: A Comprehensive Framework for High-Performance and Lightweight Scalability in Surface Code Communication.

[BibT_eX]

[DOI]

Sunghye Park

Dohun Kim

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Optimizing Ternary Multiplier Design With Fast Ternary Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers.

[BibT_eX]

[DOI]

CoRR, 2023

Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization.

[BibT_eX]

[DOI]

Seonghyeon Park

Daeyeon Kim

Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

Machine Learning-based Fast Circuit Simulation for Analog Circuit Array.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Soft Actor-Critic Reinforcement Learning-Based Optimization for Analog Circuit Sizing.

[BibT_eX]

[DOI]

Sejin Park

Youngchang Choi

Proceedings of the 20th International SoC Design Conference, 2023

Advanced Parasitic Capacitance Extraction using Active Learning.

[BibT_eX]

[DOI]

Donggyu Kim

Jakang Lee

Proceedings of the 20th International SoC Design Conference, 2023

Placement Initialization via Community Detection.

[BibT_eX]

[DOI]

Junseok Hur

Proceedings of the 20th International SoC Design Conference, 2023

Multi-Source Transfer Learning for Design Technology Co-Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Routability Prediction and Optimization Using Explainable AI.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Routability Prediction using Deep Hierarchical Classification and Regression.

[BibT_eX]

[DOI]

Daeyeon Kim

Jakang Lee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Graph Partitioning Approach for Fast Quantum Circuit Simulation.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Lightweight Speaker Recognition in Poincaré Spaces.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2022

A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping.

[BibT_eX]

[DOI]

Jihye Park

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Adaptive FSP: Adaptive Architecture Search with Filter Shape Pruning.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ACCV 2022, 2022

2021

Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Low-Power Ternary Multiplication Using Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Reinforcement Learning-Based Power Management Policy for Mobile Device Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Fluctuation-Based Fade Detection for Local Scene Changes.

[BibT_eX]

[DOI]

IEEE Access, 2021

A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Memcapacitor based Minimum and Maximum Gate Design.

[BibT_eX]

[DOI]

Jiyoung Min

Proceedings of the 18th International SoC Design Conference, 2021

Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Components Analysis on Audio Signal Mixtures.

[BibT_eX]

[DOI]

Chanhee Lee

Sangho Yoon

Proceedings of the 18th International SoC Design Conference, 2021

Data Protection Method for Flash Memory in Serial Peripheral Interface.

[BibT_eX]

[DOI]

Aeri Kim

Proceedings of the 18th International SoC Design Conference, 2021

Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Ternary Sense Amplifier Design for Ternary SRAM.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Design and Analysis of a Low-Power Ternary SRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

MDARTS: Multi-objective Differentiable Neural Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Additive Statistical Leakage Analysis Using Exponential Mixture Model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Compact Topology-Aware Bus Routing for Design Regularity.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Proactive Scenario Characteristic-Aware Online Power Management on Mobile Systems.

[BibT_eX]

[DOI]

IEEE Access, 2020

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2020

MTCMOS-based Ternary to Binary Converter.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2020

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

GRLC: grid-based run-length compression for energy-efficient CNN accelerator.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device Systems.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

SmartGrid: Video Retargeting With Spatiotemporal Grid Optimization.

[BibT_eX]

[DOI]

IEEE Access, 2019

Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems.

[BibT_eX]

[DOI]

IEEE Access, 2019

Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU.

[BibT_eX]

[DOI]

Sunghye Park

Proceedings of the 2019 International SoC Design Conference, 2019

Outlier-aware Time-multiplexing MAC for Higher Energy-Efficiency on CNNs.

[BibT_eX]

[DOI]

Eunji Kwon

Yesung Kang

Proceedings of the 2019 International SoC Design Conference, 2019

Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm.

[BibT_eX]

[DOI]

Sung-Yun Lee

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Fence-Region-Aware Mixed-Height Standard Cell Legalization.

[BibT_eX]

[DOI]

SangGi Do

Mingyu Woo

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Statistical Leakage Analysis Using Gaussian Mixture Model.

[BibT_eX]

[DOI]

IEEE Access, 2018

SoftCorner: Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems.

[BibT_eX]

[DOI]

IEEE Access, 2018

Estimation of Leakage Distribution Utilizing Gaussian Mixture Model.

[BibT_eX]

[DOI]

Hyun-jeong Kwon

Young Hwan Kim

Proceedings of the International SoC Design Conference, 2018

Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

An optimal gate design for the synthesis of ternary logic circuits.

[BibT_eX]

[DOI]

Taeho Lim

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

A Novel Ternary Multiplier Based on Ternary CMOS Compact Model.

[BibT_eX]

[DOI]

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

GRASP based metaheuristics for layout pattern classification.

[BibT_eX]

[DOI]

Mingyu Woo

Seungwon Kim

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization.

[BibT_eX]

[DOI]

Seungwon Kim

SangGi Do

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization.

[BibT_eX]

[DOI]

Sangmin Kim

Youngsoo Shin

ACM Trans. Design Autom. Electr. Syst., 2016

Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Wakeup scheduling and its buffered tree synthesis for power gating circuits.

[BibT_eX]

[DOI]

Integr., 2016

Skew control methodology for useful-skew implementation.

[BibT_eX]

[DOI]

SangGi Do

Seungwon Kim

Proceedings of the International SoC Design Conference, 2016

Novel approximate synthesis flow for energy-efficient FIR filter.

[BibT_eX]

[DOI]

Yesung Kang

Jaewoo Kim

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

An Improved Methodology for Resilient Design Implementation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

An optimal operating point by using error monitoring circuits with an error-resilient technique.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

2014

A new methodology for reduced cost of resilience.

[BibT_eX]

[DOI]

Jiajia Li

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Low-Power Integrated-Circuit Implementation Exploiting System and Application Information /

[BibT_eX]

[DOI]

PhD thesis, 2013

Enhancing the Efficiency of Energy-Constrained DVFS Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Many-Core Token-Based Adaptive Power Gating.

[BibT_eX]

[DOI]

Tajana Simunic Rosing

Richard D. Strong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Learning-based approximation of interconnect delay and slew in signoff timing tools.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Statistical analysis and modeling for error composition in approximate computation circuits.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

High-performance gate sizing with a signoff timer.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Active-mode leakage reduction with data-retained power gating.

[BibT_eX]

[DOI]

Bongil Park

Proceedings of the Design, Automation and Test in Europe, 2013

Smart non-default routing for clock power reduction.

[BibT_eX]

[DOI]

Hyein Lee

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Construction of realistic gate sizing benchmarks with known optimal solutions.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

TAP: token-based adaptive power gating.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Sensitivity-guided metaheuristics for accurate discrete gate sizing.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

MAPG: Memory access power gating.

[BibT_eX]

[DOI]

Kwangok Jeong

Tajana Simunic Rosing

Richard D. Strong

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Accuracy-configurable adder for approximate arithmetic designs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010

Toward effective utilization of timing exceptions in design optimization.

[BibT_eX]

[DOI]

Kwangok Jeong