Seok-Bum Ko

Orcid: 0000-0002-9287-317X

According to our database1, Seok-Bum Ko authored at least 162 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Unraveling the complexity: deep learning for imbalanced retinal lesion detection and multi-disease identification.
Netw. Model. Anal. Health Informatics Bioinform., December, 2024

Res-MGCA-SE: a lightweight convolutional neural network based on vision transformer for medical image classification.
Neural Comput. Appl., October, 2024

Anterior mediastinal nodular lesion segmentation from chest computed tomography imaging using UNet based neural network with attention mechanisms.
Multim. Tools Appl., May, 2024

Decoder Reduction Approximation Scheme for Booth Multipliers.
IEEE Trans. Computers, March, 2024

A Long Short-Term Memory-Based Interconnected Architecture for Classification of Grasp Types Using Surface-Electromyography Signals.
IEEE Trans. Artif. Intell., January, 2024

Deep learning-based age estimation from chest CT scans.
Int. J. Comput. Assist. Radiol. Surg., January, 2024

Probability-based mapping approach for an application-aware networks-on-chip architectures.
Nano Commun. Networks, 2024

RibFractureSys: A gem in the face of acute rib fracture diagnoses.
Comput. Medical Imaging Graph., 2024

Enhancing welfare assessment: Automated detection and imaging of dorsal and lateral views of swine carcasses for identification of welfare indicators.
Comput. Electron. Agric., 2024

Optimized Transformer Models: ℓ′ BERT with CNN-like Pruning and Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Energy Efficient FPGA-Based Binary Transformer Accelerator for Edge Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
DReD-A Descriptive Relation Dataset for Expanding Relation Extraction.
IEEE Trans. Artif. Intell., December, 2023

Residual Skip Network-Based Super-Resolution for Leaf Disease Detection of Grape Plant.
Circuits Syst. Signal Process., November, 2023

Applications of deep learning to reduce the need for iodinated contrast media for CT imaging: a systematic review.
Int. J. Comput. Assist. Radiol. Surg., October, 2023

An automated multi-class skin lesion diagnosis by embedding local and global features of Dermoscopy images.
Multim. Tools Appl., September, 2023

PaXNet: Tooth segmentation and dental caries detection in panoramic X-ray using ensemble transfer learning and capsule classifier.
Multim. Tools Appl., July, 2023

Booth Encoding-Based Energy Efficient Multipliers for Deep Learning Systems.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Histopathological carcinoma classification using parallel, cross-concatenated and grouped convolutions deep neural network.
Int. J. Imaging Syst. Technol., May, 2023

SaHNoC: an optimal energy efficient hybrid networks-on-chip architecture.
J. Supercomput., April, 2023

Non-Bianisotropic Complementary Split Ring Resonator Metamaterial Bandstop Filter Using Cylindrical Metal Vias.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Efficient Approximate Posit Multipliers for Deep Learning Computation.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

An Optimized Hardware Implementation of Modular Multiplication of Binary Ring LWE.
IEEE Trans. Emerg. Top. Comput., 2023

Interpretability of artificial intelligence models that use data fusion to predict yield in aeroponics.
J. Ambient Intell. Humaniz. Comput., 2023

2022
An efficient modeling attack for breaking the security of XOR-Arbiter PUFs by using the fully connected and long-short term memory.
Microprocess. Microsystems, October, 2022

SMA: A constructive partitioning based mapping approach for Networks-on-Chip.
Microprocess. Microsystems, October, 2022

Mixed explosives dataset.
Dataset, May, 2022

Joint restoration convolutional neural network for low-quality image super resolution.
Vis. Comput., 2022

Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Secure Covid-19 Electronic Health Records Management for Telediagnosis and Travel Ticket Assistant System Using Cryptographic Approaches.
SN Comput. Sci., 2022

Capsule GAN for prostate MRI super-resolution.
Multim. Tools Appl., 2022

COVID-CXNet: Detecting COVID-19 in frontal chest X-ray images using deep learning.
Multim. Tools Appl., 2022

A hardware accelerator for IEEE 802.15.4 Time-Slotted Channel Hopping transceiver.
Microelectron. J., 2022

FRDS: An efficient unique on-Chip interconnection network architecture.
Integr., 2022

Segmentation for document layout analysis: not dead yet.
Int. J. Document Anal. Recognit., 2022

Factorized multi-scale multi-resolution residual network for single image deraining.
Appl. Intell., 2022

Optimizing a Multispectral-Images-Based DL Model, Through Feature Selection, Pruning and Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Lightweight and CCA2-Secure Hardware Implementation of Binary Ring-LWE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Early Fault Detection of Medium Voltage Covered Conductors with Deep Learning Method.
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2022

Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications.
Proceedings of the Approximate Computing, 2022

Approximate Computing for Efficient Neural Network Computation: A Survey.
Proceedings of the Approximate Computing, 2022

Efficient Approximate DNN Accelerators for Edge Devices: An Experimental Study.
Proceedings of the Approximate Computing, 2022

2021
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Enhancing the Utilization of Processing Elements in Spatial Deep Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Area and power efficient post-quantum cryptosystem for IoT resource-constrained devices.
Microprocess. Microsystems, 2021

Energy efficient spiking neural network processing using approximate arithmetic units and variable precision weights.
J. Parallel Distributed Comput., 2021

Design of quantum-dot cellular automata-based communication system using modular N-bit binary to gray and gray to binary converters.
Int. J. Commun. Syst., 2021

Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology.
IET Comput. Digit. Tech., 2021

High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block.
IEEE Embed. Syst. Lett., 2021

Assessing the speed-accuracy trade-offs of popular convolutional neural networks for single-crop rib fracture classification.
Comput. Medical Imaging Graph., 2021

An Optimised Multivariable Regression Model for Predictive Analysis of Diabetic Disease Progression.
IEEE Access, 2021

Efficient Multiple-Precision Posit Multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Identifying Useful Features in Multispectral Images with Deep Learning for Optimizing Wheat Yield Prediction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Design of Power Efficient Posit Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Novel Architecture for Early Detection of Negative Output Features in Deep Neural Network Accelerators.
IEEE Trans. Circuits Syst., 2020

New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference.
IEEE Trans. Computers, 2020

Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders.
IEEE Trans. Computers, 2020

Blind compression artifact reduction using dense parallel convolutional neural network.
Signal Process. Image Commun., 2020

Capsule GAN for robust face super resolution.
Multim. Tools Appl., 2020

Novel convolutional neural network architecture for improved pulmonary nodule classification on computed tomography.
Multidimens. Syst. Signal Process., 2020

Efficient Hybrid CMOS/Memristor Implementation of Bidirectional Associative Memory Using Passive Weight Array.
Microelectron. J., 2020

Wavelet based medical image super resolution using cross connected residual-in-dense grouped convolutional neural network.
J. Vis. Commun. Image Represent., 2020

Power efficient error correction coding for on-chip interconnection links.
IET Comput. Digit. Tech., 2020

High throughput and area-efficient FPGA implementation of AES for high-traffic applications.
IET Comput. Digit. Tech., 2020

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems.
IEEE Embed. Syst. Lett., 2020

Deep dilated and densely connected parallel convolutional groups for compression artifacts reduction.
Digit. Signal Process., 2020

An Improved Low-Power Coding for Serial Network-On-Chip Links.
Circuits Syst. Signal Process., 2020

PaXNet: Dental Caries Detection in Panoramic X-ray using Ensemble Transfer Learning and Capsule Classifier.
CoRR, 2020

A Secure Deep Probabilistic Dynamic Thermal Line Rating Prediction.
CoRR, 2020

COVID-CXNet: Detecting COVID-19 in Frontal Chest X-ray Images using Deep Learning.
CoRR, 2020

Early detection of ankylosing spondylitis using texture features and statistical machine learning, and deep learning, with some patient age analysis.
Comput. Medical Imaging Graph., 2020

Residual learning based densely connected deep dilated network for joint deblocking and super resolution.
Appl. Intell., 2020

Ensemble Learning for Improving Generalization in Aeroponics Yield Prediction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Automated Teeth Extraction from Dental Panoramic X-Ray Images using Genetic Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Epipolar Geometry on Drones Cameras for Swarm Robotics Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support.
IEEE Trans. Computers, 2019

Design and Analysis of Area and Power Efficient Approximate Booth Multipliers.
IEEE Trans. Computers, 2019

Efficient spiking neural network training and inference with reduced precision memory and computing.
IET Comput. Digit. Tech., 2019

KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC.
IET Comput. Digit. Tech., 2019

A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption.
IEEE Access, 2019

Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Design of Approximate Restoring Dividers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Low-Cost 2-D Map Generation System for a Mobile Robot.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Energy-Efficient Approximate MAC Unit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Improved Hybrid Memory Cube for Weight-Sharing Deep Convolutional Neural Networks.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Approximate Sum-of-Products Designs Based on Distributed Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Flexible elliptic curve cryptography coprocessor using scalable finite field arithmetic blocks on FPGAs.
Microprocess. Microsystems, 2018

High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA.
IET Comput. Digit. Tech., 2018

Retinal blood vessel segmentation using fully convolutional network with transfer learning.
Comput. Medical Imaging Graph., 2018

Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An FPGA-based Closed-loop Approach of Angular Displacement for a Resolver-to-Digital-Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Power Efficient Approximate Booth Multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Design of Power and Area Efficient Approximate Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA.
IET Comput. Digit. Tech., 2017

2016
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Parallelization of scalable elliptic curve cryptosystem processors in GF(2<sup>m</sup>).
Microprocess. Microsystems, 2016

Design of a novel energy efficient topology for maximum magnitude generator.
IET Comput. Digit. Tech., 2016

Decimal floating-point fused multiply-add with redundant internal encodings.
IET Comput. Digit. Tech., 2016

2015
Bandwidth-aware routing and admission control for efficient video streaming over MANETs.
Wirel. Networks, 2015

Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
Area Efficient Sequential Decimal Fixed-point Multiplier.
J. Signal Process. Syst., 2014

Improved GPU SIMD control flow efficiency via hybrid warp size mechanism.
Microprocess. Microsystems, 2014

Design and verification of an efficient WISHBONE-based network interface for network on chip.
Comput. Electr. Eng., 2014

CARM: Congestion Adaptive Routing Method for On Chip Networks.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

FPGA implementation of low latency scalable Elliptic Curve Cryptosystem processor in GF(2<sup>m</sup>).
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

High-speed FFT processors based on redundant number systems.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Highly adaptive and congestion-aware routing for 3D NoCs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A novel hybrid topology for Network on Chip.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

QaMC - QoS Aware Multicast router for NoC fabric.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2013
Decimal Division Algorithms: The Issue of Partial Remainders.
J. Signal Process. Syst., 2013

High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings.
IEEE Trans. Computers, 2013

High performance scalable elliptic curve cryptosystem processor for Koblitz curves.
Microprocess. Microsystems, 2013

High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip.
J. Low Power Electron., 2013

Decimal SRT Square Root: Algorithm and Architecture.
Circuits Syst. Signal Process., 2013

Dynamic partial reconfigurable Viterbi decoder for wireless standards.
Comput. Electr. Eng., 2013

Noninvasive cuffless blood pressure estimation using pulse transit time and Hilbert-Huang transform.
Comput. Electr. Eng., 2013

High performance scalable elliptic curve cryptosystem processor in GF(2<sup>m</sup>).
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Reconfigurable distributed fault tolerant routing algorithm for on-chip networks.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Dynamic partial reconfigurable adaptive transceiver for OFDM based cognitive radio.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

Design of a low power network interface for Network on chip.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

Decimal signed digit addition using stored transfer encoding.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012
Improved Decimal Floating-Point Logarithmic Converter Based on Selection by Rounding.
IEEE Trans. Computers, 2012

A dynamic non-uniform segmentation method for first-order polynomial function evaluation.
Microprocess. Microsystems, 2012

Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture.
IET Comput. Digit. Tech., 2012

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems.
Circuits Syst. Signal Process., 2012

A Novel Decimal Logarithmic Converter Based on First-Order Polynomial Approximation.
Circuits Syst. Signal Process., 2012

Efficient color space-based compression scheme for endoscopic images.
Proceedings of the 11th International Conference on Information Science, 2012

High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers.
Proceedings of the International Symposium on Electronic System Design, 2012

Improved Design of High-Radix Signed-Digit Adders.
Proceedings of the International Symposium on Electronic System Design, 2012

Improvements for High Performance Elliptic Curve Cryptosystem Processor over GF(2^163).
Proceedings of the International Symposium on Electronic System Design, 2012

GPU-based Parallel Implementation of SAR Imaging.
Proceedings of the International Symposium on Electronic System Design, 2012

Design and implementation of a Radix-100 division unit.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-power subsample-based image compression algorithm for capsule endoscopy.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

High-frequency sequential decimal multipliers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Improvements on the design and implementation of DVB-S2 LDPC decoders.
Comput. Electr. Eng., 2011

Lossless implementation of Daubechies 8-tap wavelet transform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Nonspeculative decimal signed digit adder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An efficient YUV-based image compression algorithm for wireless capsule endoscopy.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

A heart rate sensor based on seismocardiography for vital sign monitoring systems.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
A high performance ECC hardware implementation with instruction-level parallelism over GF(2<sup>163</sup>).
Microprocess. Microsystems, 2010

Hybrid Architecture and VLSI Implementation of the Cosine-Fourier-Haar Transforms.
Circuits Syst. Signal Process., 2010

A high performance pseudo-multi-core ECC processor over GF(2<sup>163</sup>).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel scalable parallel architecture for biological neural simulations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.
EURASIP J. Embed. Syst., 2009

Efficient Hardware Implementation of Hybrid Cosine-fourier-wavelet Transforms on a Single FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A New Decimal Antilogarithmic Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 32-bit Decimal Floating-Point Logarithmic Converter.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
A novel decimal-to-decimal logarithmic converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Efficient hardware implementation of an image compressor for wireless capsule endoscopy applications.
Proceedings of the International Joint Conference on Neural Networks, 2008

Convergence Analysis of Jacobi Iterative Method Using Logarithmic Number System.
Proceedings of the 7th IEEE/ACIS International Conference on Computer and Information Science, 2008

2006
A Study on the Floating-Point Adder in FPGAS.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

FPGA Implementation of a Face Detector using Neural Networks.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Effect of Postural Changes on Baroreflex Sensitivity: A study on the Eurobavar data set.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2004
Efficient Realization of Parity Prediction Functions in FPGAs.
J. Electron. Test., 2004

Area Minimization of Exclusive-OR Intensive Circuits in FPGAs.
J. Electron. Test., 2004

2003
A Novel Technology Mapping Method for AND/XOR Expressions.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002
Studies of the SEMATECH IDDq test data.
J. Syst. Archit., 2002

Efficient Decomposition Techniques for FPGAs.
Proceedings of the High Performance Computing, 2002

2001
Efficient Parity Prediction in FPGA.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001


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