Senling Wang

According to our database, Senling Wang authored at least 28 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers.

Qingsong Peng, Jingchang Bian, Zhengfeng Huang, Senling Wang, Aibin Yan

ACM Trans. Design Autom. Electr. Syst., January, 2024

Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device.

Xihong Zhou, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi

IEICE Trans. Inf. Syst., January, 2024

A demultiplexer-based dual-path switching true random number generator.

Tianming Ni, Kejie Xu, Hao Wu, Senling Wang, Mu Nie

Microelectron. J., 2024

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs.

Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness.

Tianming Ni, Qingsong Peng, Jingchang Bian, Liang Yao, Zhengfeng Huang, Aibin Yan, Senling Wang, Xiaoqing Wen

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Test Point Insertion for Multi-Cycle Power-On Self-Test.

Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

ACM Trans. Design Autom. Electr. Syst., 2023

SASL-JTAG: A Light-Weight Dependable JTAG.

Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning.

Mu Nie, Wen Jiang, Wankou Yang, Senling Wang, Xiaoqing Wen, Tianming Ni

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges.

Tianming Ni, Fei Li, Qingsong Peng, Senling Wang, Xiaoqing Wen

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

QR-Code with Superimposed Text.

Naoya Tahara, Senling Wang, Hiroshi Kai, Hiroshi Takahashi, Masakatu Morii

Proceedings of the 24st Asia-Pacific Network Operations and Management Symposium, 2023

2022

Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation.

Tsutomu Inamoto, Tomoki Nishino, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2020

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips.

Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen

IEEE Trans. Emerg. Top. Comput., 2020

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST.

Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

IEICE Trans. Inf. Syst., 2020

2018

Automotive Functional Safety Assurance by POST with Sequential Observation.

Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima

IEEE Des. Test, 2018

Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.

Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

Proceedings of the 23rd IEEE European Test Symposium, 2018

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.

Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

Proceedings of the 27th IEEE Asian Test Symposium, 2018

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST.

Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line.

Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

IEICE Trans. Inf. Syst., 2017

Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD).

Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays.

Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

IPSJ Trans. Syst. LSI Des. Methodol., 2016

Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation.

Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima

Proceedings of the 25th IEEE Asian Test Symposium, 2016

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST.

Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip.

Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi

J. Low Power Electron., 2015

Diagnosis of Delay Faults Considering Hazards.

Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2013

Scan-Out Power Reduction for Logic BIST.

Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase

IEICE Trans. Inf. Syst., 2013

2012

A Scan-Out Power Reduction Method for Multi-cycle BIST.

Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Low Power BIST for Scan-Shift and Capture Power.

Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Genetic algorithm based approach for segmented testing.

Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011