Seiya Tanikawa

According to our database, Seiya Tanikawa authored at least 3 papers between 2013 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors.

Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC.

Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.

Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013