Seiya Shibata

According to our database1, Seiya Shibata authored at least 12 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
PREDEA: Predicted-RoI based Resource-Efficient Object Detection with Aggregation.
Proceedings of the IEEE International Conference on Smart Computing, 2024

2022
RegionDrop: Fast Human Pose Estimation Using Annotation-Aware Spatial Sparsity.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2022, 2022

2019
Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA.
IPSJ Trans. Syst. LSI Des. Methodol., 2019

Real-Time Detection and Tracking Using Hybrid DNNs and Space-Aware Color Feature: From Algorithm to System.
Proceedings of the Pattern Recognition - 5th Asian Conference, 2019

2014
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

2012
A Fast Performance Estimation Framework for System-Level Design Space Exploration.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

2011
Fast design space exploration for mixed hardware-software embedded systems.
Proceedings of the International SoC Design Conference, 2011

2010
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Automatic communication synthesis with hardware sharing for design space exploration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
Embedded System Covalidation with RTOS Model and FPGA.
IPSJ Trans. Syst. LSI Des. Methodol., 2008


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