Seiji Kajihara

According to our database, Seiji Kajihara authored at least 154 papers between 1991 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Area Efficient 0.009-mm² 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator.

Joshua Adiel Wijaya, Poki Chen, Lucky Kumar Pradhan, Ahmad Shahid Bhatti, Seiji Kajihara

IEEE Trans. Very Large Scale Integr. Syst., October, 2024

2022

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection.

Poki Chen, Joshua Adiel Wijaya, Seiji Kajihara, Trio Adiono, Hsiang-Yu Chen, Ruei-Ting Wang, Yousuke Miyake

IEEE Access, 2022

A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications.

Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara

Proceedings of the IEEE International Test Conference, 2022

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits.

Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2022

On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and Prediction.

Takaaki Kato, Yousuke Miyake, Seiji Kajihara

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.

Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

IEICE Trans. Inf. Syst., 2021

2020

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters.

Poki Chen, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui, John Carl Joel Salao Marquez, Seiji Kajihara, Yousuke Miyake

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips.

Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen

IEEE Trans. Emerg. Top. Comput., 2020

Innovative Test Practices in Asia.

Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Path Delay Measurement with Correction for Temperature And Voltage Variations.

Yousuke Miyake, Takaaki Kato, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2020

On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test.

Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor.

Masayuki Gondo, Yousuke Miyake, Takaaki Kato, Seiji Kajihara

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

On-Chip Delay Measurement for In-Field Test of FPGAs.

Yousuke Miyake, Yasuo Sato, Seiji Kajihara

Proceedings of the 24th IEEE Pacific Rim International Symposium on Dependable Computing, 2019

A Static Method for Analyzing Hotspot Distribution on the LSI.

Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2019

A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor.

Yousuke Miyake, Yasuo Sato, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2019

On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs.

Yousuke Miyake, Seiji Kajihara, Poki Chen

Proceedings of the IEEE International Test Conference in Asia, 2019

FPGA implementation of ECDSA for Blockchain.

Shoi Tachibana, Shunsuke Araki, Seiji Kajihara, Shigeyuki Azuchi, Yukishige Nakajo, Hideki Shoda

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2018

Good Die Prediction Modelling from Limited Test Items.

Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura

Proceedings of the IEEE International Test Conference in Asia, 2018

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing.

Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian

Proceedings of the 27th IEEE Asian Test Symposium, 2018

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST.

Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Analysis and mitigation or IR-Drop induced scan shift-errors.

Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

Proceedings of the IEEE International Test Conference, 2017

On the effects of real time and contiguous measurement with a digital temperature and voltage sensor.

Yousuke Miyake, Yasuo Sato, Seiji Kajihara

Proceedings of the International Test Conference in Asia, 2017

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.

Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor.

Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura

IEEE Trans. Very Large Scale Integr. Syst., 2016

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation.

Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST.

Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test.

Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip.

Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi

J. Low Power Electron., 2015

Identification of high power consuming areas with gate type and logic level information.

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 20th IEEE European Test Symposium, 2015

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

IEICE Trans. Inf. Syst., 2014

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA.

Yasuo Sato, Masafumi Monden, Yousuke Miyake, Seiji Kajihara

Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test.

Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories.

Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

An On-Chip Digital Environment Monitor for Field Test.

Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Scan-Out Power Reduction for Logic BIST.

Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase

IEICE Trans. Inf. Syst., 2013

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing.

Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara

IEICE Trans. Inf. Syst., 2013

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing.

Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte

IEEE Des. Test, 2013

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.

Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

Proceedings of the 22nd Asian Test Symposium, 2013

A Stochastic Model for NBTI-Induced LSI Degradation in Field.

Yasuo Sato, Seiji Kajihara

Proceedings of the 22nd Asian Test Symposium, 2013

Search Space Reduction for Low-Power Test Generation.

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 22nd Asian Test Symposium, 2013

2012

A Failure Prediction Strategy for Transistor Aging.

Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara

IEEE Trans. Very Large Scale Integr. Syst., 2012

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.

Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On pinpoint capture power management in at-speed scan test generation.

Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

Proceedings of the 2012 IEEE International Test Conference, 2012

DART: Dependable VLSI test architecture and its implementation.

Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura

Proceedings of the 2012 IEEE International Test Conference, 2012

On-chip temperature and voltage measurement for field testing.

Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara

Proceedings of the 17th IEEE European Test Symposium, 2012

A Scan-Out Power Reduction Method for Multi-cycle BIST.

Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Low Power BIST for Scan-Shift and Capture Power.

Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Delay Testing: Improving Test Quality and Avoiding Over-testing.

Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda

IPSJ Trans. Syst. LSI Des. Methodol., 2011

A GA-Based <i>X</i>-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

IEICE Trans. Inf. Syst., 2011

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

IEICE Trans. Inf. Syst., 2011

Power-aware test generation with guaranteed launch safety for at-speed scan testing.

Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A novel scan segmentation design method for avoiding shift timing failure in scan testing.

Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang

Proceedings of the 2011 IEEE International Test Conference, 2011

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.

Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Genetic algorithm based approach for segmented testing.

Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

Transition-Time-Relation based capture-safety checking for at-speed scan test generation.

Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara

Proceedings of the Design, Automation and Test in Europe, 2011

Multi-cycle Test with Partial Observation on Scan-Based BIST Structure.

Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.

Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

On Delay Test Quality for Test Cubes.

Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen

IPSJ Trans. Syst. LSI Des. Methodol., 2010

A Study of Capture-Safe Test Generation Flow for At-Speed Testing.

Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.

Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

IEICE Trans. Inf. Syst., 2010

Aging test strategy and adaptive test scheduling for SoC failure prediction.

Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

On estimation of NBTI-Induced delay degradation.

Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura

Proceedings of the 15th European Test Symposium, 2010

2009

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.

Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.

Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Estimation of Delay Test Quality and Its Application to Test Generation.

Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo

IPSJ Trans. Syst. LSI Des. Methodol., 2008

A Novel Per-Test Fault Diagnosis Method Based on the Extended <i>X</i>-Fault Model for Deep-Submicron LSI Circuits.

Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara

IEICE Trans. Inf. Syst., 2008

On Detection of Bridge Defects with Stuck-at Tests.

Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy

IEICE Trans. Inf. Syst., 2008

Special Section on Test and Verification of VLSIs.

Seiji Kajihara, Michiko Inoue

IEICE Trans. Inf. Syst., 2008

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

J. Electron. Test., 2008

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja

Proceedings of the 13th European Test Symposium, 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.

Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

A Novel ATPG Method for Capture Power Reduction during Scan Testing.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2007

A novel scheme to reduce power supply noise for high-quality at-speed scan testing.

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang

Proceedings of the 2007 IEEE International Test Conference, 2007

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja

Proceedings of the 44th Design Automation Conference, 2007

2006

A New Method for Low-Capture-Power Test Generation for Scan Testing.

Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2006

A Per-Test Fault Diagnosis Method Based on the <i>X</i>-Fault Model.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2006

A Statistical Quality Model for Delay Testing.

Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara

IEICE Trans. Electron., 2006

On Finding Don't Cares in Test Sequences for Sequential Circuits.

Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu

IEICE Trans. Inf. Syst., 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Framework of High-quality Transition Fault ATPG for Scan Circuits.

Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato

Proceedings of the 2006 IEEE International Test Conference, 2006

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A dynamic test compaction procedure for high-quality path delay testing.

Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Test cost reduction for logic circuits: Reduction of test data volume and test application time.

Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu

Syst. Comput. Jpn., 2005

Efficient Test Set Modification for Capture Power Reduction.

Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja

J. Low Power Electron., 2005

On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.

Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2005

On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis.

Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka

IEICE Trans. Inf. Syst., 2005

On Low-Capture-Power Test Generation for Scan Testing.

Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.

Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Low-capture-power test generation for scan-based at-speed testing.

Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Invisible delay quality - SDQM model lights up what could not be seen.

Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Path delay test compaction with process variation tolerance.

Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato

Proceedings of the 42nd Design Automation Conference, 2005

On Improving Defect Coverage of Stuck-at Fault Tests.

Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Evaluation of the statistical delay quality model.

Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.

Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

XID: Don't care identification of test patterns for combinational circuits.

Kohei Miyase, Seiji Kajihara

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Don't Care Identification and Statistical Encoding for Test Data Compression.

Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy

IEICE Trans. Inf. Syst., 2004

Random Access Scan: A solution to test power, test data volume and test time.

Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On per-test fault diagnosis using the X-fault model.

Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.

Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy

Proceedings of the 9th European Test Symposium, 2004

Multiple Scan Tree Design with Test Vector Modification.

Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction.

Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

On test data volume reduction for multiple scan chain designs.

Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz

ACM Trans. Design Autom. Electr. Syst., 2003

BIST-oriented test pattern generator for detection of transition faults.

Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara

Syst. Comput. Jpn., 2003

Evaluation of Delay Testing Based on Path Selection.

Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

On Selecting Testable Paths in Scan Designs.

Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara

J. Electron. Test., 2003

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume.

Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.

Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Optimal Scan Tree Construction with Test Vector Modification for Test Compression.

Kohei Miyase, Seiji Kajihara

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

On Estimation of Fault Efficiency for Path Delay Faults.

Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

On effective criterion of path selection for delay testing.

Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Test Vector Modification for Power Reduction during Scan Testing.

Seiji Kajihara, Koji Ishida, Kohei Miyase

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.

Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Don't-Care Identification on Specific Bits of Test Patterns.

Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A Method of Static Test Compaction Based on Don't Care Identification.

Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Data Compression Using Don't-Care Identification and Statistical Encoding.

Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Data Compression Using Don?t-Care Identification and Statistical Encoding.

Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits.

Seiji Kajihara, Kohei Miyase

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

An Efficient Method to Identify Untestable Path Delay Faults.

Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Hybrid BIST Using Partially Rotational Scan.

Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

On validating data hold times for flip-flops in sequential circuits.

Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Selection of potentially testable path delay faults for test generation.

Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Enhanced untestable path analysis using edge graphs.

Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

On Test Generation with A Limited Number of Tests.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits.

Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

On Test Pattern Compaction Using Random Pattern Fault Simulation.

Seiji Kajihara, Kewal K. Saluja

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.

Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Compact test sets for high defect coverage.

Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A diagnosis method for single logic design errors in gate-level combinational circuits.

Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita

Syst. Comput. Jpn., 1997

On invariant implication relations for removing partial circuits.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Syst. Comput. Jpn., 1997

Synthesis of Sequential Circuits by Redundancy Removal and Retiming.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

J. Electron. Test., 1997

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.

Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

On the Adders with Minimum Tests.

Seiji Kajihara, Tsutomu Sasao

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

On the effects of test compaction on defect coverage.

Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.

Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

IEICE Trans. Inf. Syst., 1995

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis.

Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita

IEICE Trans. Inf. Syst., 1995

Partial scan design and test sequence generation based on reduced scan shift method.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

J. Electron. Test., 1995

Resynthesis for sequential circuits designed with a specified initial state.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Compact test generation for bridging faults under I_DDQ testing.

Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis for Testability by Sequential Redundancy Removal Using Retiming.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Digest of Papers: FTCS-25, 1995

Test sequence compaction by reduced scan shift and retiming.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

On compacting test sets by addition and removal of test vectors.

Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Reduced Scan Shift: A New Testing Method for Sequential Circuit.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993

Removal of redundancy in combinational circuits under classification of undetectable faults.

Seiji Kajihara, Kozo Kinoshita, Haruko Shiba

Syst. Comput. Jpn., 1993

Test generation for multiple faults based on parallel vector pair analysis.

Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults.

Seiji Kajihara, Haruko Shiba, Kozo Kinoshita

Proceedings of the Digest of Papers: FTCS-22, 1992

1991

Stuck-open faults test generation for cmos combinational circuits.

Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita

Syst. Comput. Jpn., 1991