Seiichi Aritome

According to our database, Seiichi Aritome authored at least 6 papers between 1989 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Array Architectures for 3-D NAND Flash Memories.

Rino Micheloni, Seiichi Aritome, Luca Crippa

Proc. IEEE, 2017

Study of error repeatability and recovery in 40nm TaOx ReRAM.

Takashi Inose, Seiichi Aritome, Ryutaro Yasuhara, Satoshi Mishima, Ken Takeuchi

Proceedings of the 47th European Solid-State Device Research Conference, 2017

1999

A 130-mm/², 256-Mbit NAND flash with shallow trench isolation technology.

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui

IEEE J. Solid State Circuits, 1999

1997

A compact on-chip ECC for low cost flash memories.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi

IEEE J. Solid State Circuits, 1997

1993

Reliability issues of flash memory cells.

Seiichi Aritome, Riichiro Shirota, Gertjan Hemink, Tetsuo Endoh, Fujio Masuoka

Proc. IEEE, 1993

1989

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell.

Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka

IEEE J. Solid State Circuits, October, 1989