Sei Seung Yoon
According to our database1,
Sei Seung Yoon
authored at least 10 papers
between 2008 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm<sup>2</sup> at 0.60V for Auto-G1 Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2014
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors.
Proceedings of the 2014 International Test Conference, 2014
Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Experiments and analysis to characterize logic state retention limitations in 28nm process node.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2011
Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the 45th Design Automation Conference, 2008